MAXQ7670EVKIT+ Maxim Integrated Products, MAXQ7670EVKIT+ Datasheet - Page 26

• Manufacturer Part Number: MAXQ7670EVKIT+
• Description: KIT EVAL FOR MAXQ7670
• Manufacturer: Maxim Integrated Products
• Series: MAXQ®r
• Type: MCUr

Specifications of MAXQ7670EVKIT+

• Contents: Board
• For Use With/related Products: MAXQ7670
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
The drive capability of the I/O, when configured for out-
put, depends on the value in the PS0 (pad drive
strength) register and can be set for either 1mA or
2mA. When an I/O is configured as an input, writing to
the PO register enables/disables the pullup/pulldown
resistor. The value in the PRO (pad resistive pull direc-
tion) register sets the enabled resistor at the I/O as
either a pullup to DVDDIO or pulldown to GNDIO.
Refer to the MAXQ7670 User’s Guide for more detailed
information.
The MAXQ7670 includes a bidirectional 7-bit I/O port
(P0) whose features include:
• Schmitt trigger input circuitry with software-selectable
• Software-selectable push-pull CMOS output drivers
• Falling or rising edge interrupt capability
• P0.4, P0.6, and P0.7 I/Os contain an additional special
• Selectable pad drive strength and resistive pull direction
Refer to the MAXQ7670 User’s Guide for more details.
Figure 11 illustrates the functional blocks of an I/O.
Figure 11. Digital I/O Circuitry
26
high-impedance or weak pullup to DVDDIO or pull-
down to GNDIO
capable of sinking and sourcing 0.5mA
function, such as a logic input/output for a timer channel
PD0._
PO0._
PO0._
PD0._
PR0._
PS0._
PI0._
______________________________________________________________________________________
MAXQ7670
PULLDOWN
PULLUP/
LOGIC
Port Characteristics
V
DVDDIO
P
N
P0._
The MAXQ7670’s core is a member of the low-cost,
high-performance, CMOS, fully static, 16-bit MAXQ20
core µCs. The MAXQ7670 is structured on a highly
advanced, accumulator-based, 16-bit RISC architec-
ture. Fetch and execution operations complete in one
cycle without pipelining because the instruction con-
tains both the op code and data. The result is a stream-
lined 1 million instructions-per-second-per-megahertz
(MIPS/MHz) µC.
The highly efficient core is supported by a 16-level
hardware stack, enabling fast subroutine calling and
task switching. The internal data pointers manipulate
data quickly and efficiently. Multiple data pointers allow
more than one function to access data memory without
having to save and restore data pointers each time. The
data pointers can automatically increment or decre-
ment following an operation, eliminating the need for
software intervention and increasing application speed.
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The highly orthogonal instruction set allows arith-
metic and logical operations to use any register along
with the accumulator. Special-function registers (also
called peripheral registers) control the peripherals and
are subdivided into register modules. The modular fam-
ily architecture allows new devices and modules to
reuse code developed for existing products. The archi-
tecture is transport-triggered. This means that writes or
reads from certain register locations can also cause
side effects to occur. These side effects form the basis
for the higher-level op codes defined by the assembler,
such as ADDC, OR, JUMP, etc.
The MAXQ7670 incorporates the following memory
areas (see Figure 12):
• 8KB (4K x 16) utility ROM
• 64KB (32K x 16) of flash memory for program storage
• 2048 bytes (1024 x 16) of SRAM for storage of tempo-
• 16-level stack memory for storage of program return
A 16-bit-wide x 16 deep internal hardware stack pro-
vides storage for program return addresses and gener-
al-purpose use. The MAXQ7670 core implicitly uses the
stack when executing an interrupt service routine (ISR)
and also when running CALL, RET, and RETI instruc-
tions. The stack can also be explicitly used by the
rary variables
addresses and general-purpose use
MAXQ20 Core Architecture
Memory Organization
Instruction Set