8.10.00 J-TRACE ARM Segger Microcontroller Systems, 8.10.00 J-TRACE ARM Datasheet - Page 178

• Manufacturer Part Number: 8.10.00 J-TRACE ARM
• Description: JTAG EMULATOR ARM7/ARM9 ETM
• Manufacturer: Segger Microcontroller Systems
• Type: Emulatorr

Specifications of 8.10.00 J-TRACE ARM

• Contents: Emulation Module
• For Use With/related Products: ARM7, ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 899-1006

178
8.2.2
J-Link / J-Trace (UM08001)
The following table lists the JTAG+Trace connector pinout. It is compatible to the
"Trace Port Physical Interface" described in [ETM], 8.2.2 "Single target connector
pinout".
Table 8.5: JTAG+Trace connector pinout
10
11
12
13
14
15
16
17
18
19
20
21
PIN
1
2
3
4
5
6
7
8
9
Pinout
NC
NC
NC
NC
GND
TRACECLK
DBGRQ
DBGACK
RESET
EXTTRIG
TDO
VTRef
RTCK
VSupply
TCK
Trace signal 12
TMS
Trace signal 11
TDI
Trace signal 10
nTRST
SIGNAL
No connected.
No connected.
No connected.
No connected.
Signal ground.
Clocks trace data on rising edge or both edges.
Debug request.
Debug acknowledge from the test chip, high when in
debug state.
Open-collector output from the run control to the target
system reset.
Optional external trigger signal to the Embedded trace
Macrocell (ETM). Not used. Leave open on target system.
Test data output from target JTAG port.
Signal level reference. It is normally fed from Vdd of the
target board and must not have a series resistor.
Return test clock from the target JTAG port.
Supply voltage. It is normally fed from Vdd of the target
board and must not have a series resistor.
Test clock to the run control unit from the JTAG port.
Trace signal. For more information, please refer to
Assignment of trace information pins between ETM archi-
tecture versions on page 180.
Test mode select from run control to the JTAG port.
Trace signal. For more information, please refer to
Assignment of trace information pins between ETM archi-
tecture versions on page 180.
Test data input from run control to the JTAG port.
Trace signal. For more information, please refer to
Assignment of trace information pins between ETM archi-
tecture versions on page 180.
Active-low JTAG reset
CHAPTER 8
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
Description
Target interfaces and adapters