M3062PT3-CPE-1 Renesas Electronics America, M3062PT3-CPE-1 Datasheet - Page 79

• Manufacturer Part Number: M3062PT3-CPE-1
• Description: DEV COMP EMULATOR M16C/26A,28,29
• Manufacturer: Renesas Electronics America
• Type: In Circuit Debuggerr

Specifications of M3062PT3-CPE-1

• Contents: Compact Emulator, IDE, Assembler and Linker
• For Use With/related Products: M16C/26A, M16C/28, M16C/29
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

M3062PT3-CPE User’s Manual
4.2 Access Timing
Because this product emulates some ports, access timings are different from those of the actual MCUs. Chapters 4.2.1 and
4.2.2 describe the access timing using this product.
4.2.1 Operation Timing of Memory Expansion Mode and Microprocessor Mode (VCC1=VCC2=5V)
(1) Separate Bus Timing
Table 4.2 and Figure 4.1 show the bus timing in memory expansion mode and microprocessor mode (3 wait, accessing external
area).
Table 4.2 Memory expansion mode and microprocessor mode (3 wait, accessing external area)
*1 Calculated by the following formula according to the frequency of BCLK.
*2 Calculated by the following formula according to the frequency of BCLK.
*3 Calculated by the following formula according to the frequency of BCLK.
REJ10J1007-0400 Rev.4.00 July 29, 2009
(
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
f
f
n
0
0
(
(
5 .
5 .
f
−
BCLK
BCLK
(
×
×
0
BCLK
Symbol
5 .
10
10
)
9
9
×
)
)
10
−
)
8
9
[ns]
−
[ns]
40
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
[ns] n: "3" for 3 wait
Item
Min.
(*2)
(*1)
(*2)
-4
Actual MCU
0
4
0
4
0
4
[ns]
Max.
25
25
25
25
25
40
See left
See left
See left
See left
See left
See left
See left
Min.
(*3)
(*3)
4. Hardware Specifications
-4
This product
[ns]
See left
See left
See left
See left
Max.
28
28
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