ATF15XX-DK2 Atmel, ATF15XX-DK2 Datasheet - Page 16
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ATF15XX-DK2
Manufacturer Part Number
ATF15XX-DK2
Description
KIT CPLD DEVELOPMENT/PROGRAMMER
Manufacturer
Atmel
Specifications of ATF15XX-DK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Hardware Description
Table 2-8. Connections of LEDs to ATF15xx 160-lead PQFP
2.1.2
2.1.3
2-6
3300A–PLD–08/02
DSP/Sgt
1/DOT
2/DOT
1/C
1/D
1/G
2/C
2/D
2/G
1/A
1/B
1/E
1/F
2/A
2/B
2/E
2/F
Push-button
Switches
Clock Select Jumper The Clock Select Jumper, labeled JPCLK, on the CPLD Development/Programmer
PLD Pin #
91
89
90
80
73
78
72
88
69
71
68
92
94
93
96
70
DSP/Sgt
Two push-button switches are provided to allow the user to control the logic states of the
OE1 and GCLR inputs of the ATF15xx. These two switches are labeled GOE and GCLR
on the board. The GCLR push-button switch is a momentary Single-Pole Single-Throw
(SPST) normally open switch while the GOE push-button switch is a snap-acting
momentary SPST normally open switch. As shown in the CPLD Development/Program-
mer Board schematic in Figure 4-1, these two switches are normally open and the
GCLR and GOE signals are pulled-up to V
switches are depressed, the GCLR and GOE signals are connected to GND.
The output of the GCLR switch is connected to the GCLR dedicated input pin of the
ATF15xx, and it is intended to be used as an active-low reset signal to reset the regis-
ters in the ATF15xx. The output of the GOE switch is connected to the OE1 dedicated
input pin of the ATF15xx. It is intended to be used as an active-high or active-low output
enable signal to control the enabling/disabling of the tri-state output buffers in the
ATF15xx. However, these two switches can also be used to generate general logic input
signals to the GCLR and OE1 input pins of the ATF15xx.
Board is a two-position jumper that allows the user to select which GCLK dedicated
input pin (either GCLK1 or GCLK2) of the ATF15xx should be connected to the output of
the 2 MHz crystal oscillator. In addition, the jumper can be removed to allow an external
clock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx.
Table 2-9 shows the pin numbers for the GCLR, OE1, GCLK1 and GCLK2 dedicated
input pins of the ATF15xx in all the available package types.
3/DOT
4/DOT
3/C
3/D
3/G
4/C
4/D
4/G
3/A
3/B
3/E
3/F
4/A
4/B
4/E
4/F
PLD Pin #
102
100
101
103
105
106
110
108
109
123
111
121
122
107
98
97
DSP/Sgt
5/DOT
6/DOT
5/C
5/D
5/G
6/C
6/D
6/G
5/A
5/B
5/E
5/F
6/A
6/B
6/E
6/F
CPLD Development/Programmer Kit User Guide
PLD Pin #
CC
159
160
158
11
10
12
13
14
20
18
16
19
21
23
24
15
when they are not depressed. When the
DSP/Sgt
7/DOT
8/DOT
7/C
7/G
8/C
8/D
8/G
7/A
7/B
7/D
7/E
7/F
8/A
8/B
8/E
8/F
PLD Pin #
29
27
28
52
50
53
51
25
43
49
30
31
32
41
33
48