AT91CAP7A-STK Atmel, AT91CAP7A-STK Datasheet

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AT91CAP7A-STK

Manufacturer Part Number
AT91CAP7A-STK
Description
KIT STARTER FOR CAP CUSTOM MCU
Manufacturer
Atmel
Series
CAP™r
Type
MCUr
Datasheets

Specifications of AT91CAP7A-STK

Contents
Board, Cable, CD, Power Supply
Processor To Be Evaluated
AT91CAP7E
Data Bus Width
32 bit
Interface Type
USB, JTAG, SPI
For Use With/related Products
AT91CAP7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AT91CAP7E is an ARM7™-based MCU with a direct FPGA interface, six-layer advanced high-speed
bus (AHB), peripheral DMA controller and 160 Kbytes of on-chip SRAM. It offers seamless migration to
AT91CAP7 customizable MCUs for ARM7-plus-FPGA designs. It includes on-chip peripherals such as
USB 2.0 full speed device, SPI master and slave, two USARTs, three 16-bit timer counters, an 8-channel/
10-bit analog to digital converter, plus a full-functioned system controller including interrupt and power
control and supervisory functions.
The FPGA interface on the AT91CAP7E provides the FPGA with direct access to the AT91CAP7E’s
on-chip AHB and peripheral DMA controller. This architecture eliminates FPGA-induced bus contention,
off-loads MCU-to-FPGA communications from the CPU, and frees up the external bus interface for
external memory access.
Interfacing an ARM7-based MCU to an FPGA has traditionally been done through the external bus
interface (EBI) or programmable I/O. Either arrangement requires that the CPU transfer data to and from
the FPGA one word-at-a-time, basically stealing CPU cycles that should be conserved for processing and
limiting access to external memory during FPGA operations.
The FPGA interface on Atmel’s AT91CAP7E provides the FPGA with two AHB masters, four AHB slaves,
a special direct AHB slave interface to an external RAM through the FPGA, and a programmable ROM
that remaps the external RAM to emulate and debug the ROM code. Fourteen advanced peripheral bus
(APB) slaves, two full-duplex DMA channels and 32-bit programmable I/O may be hardware selected to
share I/O. An on-chip priority interrupt controller provides up to 13 encoded interrupts and two additional
un-encoded interrupts for DMA transfers.
32K OSC
RC OSC
SHWDC
System Controller
AT91CAP7E
Main
PMC
AT91CAP7E
OSC
AIC
GPBREG
WDT
POR
PLL
POR
PLL
RTT
PIT
APB
Device
USB
JTAG
ICE
FS
ARM7TDMI
ROM (256KB)
SPI
PIO
SRAM
x32
96KB
AMBA Bridge
SRAM
64KB
Timer
x3
6 -layer AHB Matrix
USART
CAP
FPGA Interface
USART
TM
CUSTOMIZABLE MICROCONTROLLERS
Peripheral DMA
ADC
Controller
NAND Flash
Static Mem.
SDRAM
EBI
CF

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AT91CAP7A-STK Summary of contents

Page 1

... FPGA one word-at-a-time, basically stealing CPU cycles that should be conserved for processing and limiting access to external memory during FPGA operations. The FPGA interface on Atmel’s AT91CAP7E provides the FPGA with two AHB masters, four AHB slaves, a special direct AHB slave interface to an external RAM through the FPGA, and a programmable ROM that remaps the external RAM to emulate and debug the ROM code ...

Page 2

... INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’ ...

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