AD9773-EB Analog Devices Inc, AD9773-EB Datasheet - Page 30

• Manufacturer Part Number: AD9773-EB
• Description: BOARD EVAL FOR AD9773
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9773-EB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 2
• Number Of Bits: 12
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 160M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9773

AD9773
TWO-PORT DATA INPUT MODE
The digital data input ports can be configured as two
independent ports or as a single (one-port mode) port. In the
two-port mode, data at the two input ports is latched into the
AD9773 on every rising edge of the data rate clock (DATACLK).
Also, in the two-port mode, the AD9773 can be programmed to
generate an externally available DATACLK for the purpose of
data synchronization. This data rate clock can be programmed to
be available at either Pin 8 (DATACLK/PLL_LOCK) or Pin 53
(SPI_SDO). Because Pin 8 can also function as a PLL lock
indicator when the PLL is enabled, there are several options for
configuring Pin 8 and Pin 53. The following information
describes the options.
PLL Off (Register 4, Bit 7 = 0)
Register 4, Bit 7 = 0; DATACLK out of Pin 8.
Register 4, Bit 7 = 1; DATACLK out of Pin 53.
PLL On (Register 4, Bit 7 = 1)
Register 4, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out
of Pin 8.
Register 4, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out
of Pin 53.
Register4, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8.
Register 4, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53.
In one-port mode, P2B14 and P2B15 from input data port two
are redefined as IQSEL and ONEPORTCLK, respectively. The
input data in one-port mode is steered to one of the two internal
data channels based on the logic level of IQSEL. A clock signal,
ONEPORTCLK, is generated by the AD9773 in this mode for
the purpose of data synchronization. ONEPORTCLK runs at
the input interleaved data rate, which is 2× the data rate at the
internal input to either channel.
Test configurations showing the various clocks that are required
and generated by the AD9773 with the PLL enabled/disabled
and in the one-port/two-port modes are given in Figure 101 to
Figure 104. Jumper positions needed to operate the AD9773
evaluation board in these modes are given as well.
Rev. D | Page 30 of 60
ONE-PORT/TWO-PORT INPUT MODES
The digital data input ports can be configured as two
independent ports or as a single (one-port mode) port. In two-
port mode, the AD9773 can be programmed to generate an
externally available data rate clock (DATACLK) for the purpose
of data synchronization. Data at the two input ports can be
latched into the AD9773 on every rising clock edge of
DATACLK. In one-port mode, P2B10 and P2B11 from Input
Data Port 2 are redefined as IQSEL and ONEPORTCLK,
respectively. The input data in one-port mode is steered to one
of the two internal data channels based on the logic level of
IQSEL. A clock signal, ONEPORTCLK, is generated by the
AD9773 in this mode for the purpose of external data
synchronization. ONEPORTCLK runs at the input interleaved
data rate, which is 2× the data rate at the internal input to either
channel.
Test configurations showing the various clocks required and
produced by the AD9773 in the PLL and one-port/two-port
modes are given in Figure 101 to Figure 104. Jumper positions
needed to operate the AD9773 evaluation board in these modes
are given as well.
PLL ENABLED, TWO-PORT MODE
(Control Register 02h, Bits [6:0] and 04h, Bits [7:1]
With the phase-locked loop (PLL) enabled and the AD9773 in
two-port mode, the speed of CLKIN is inherently that of the
input data rate. In two-port mode, Pin 8 (DATACLK/PLL_
LOCK) can be programmed (Control Register 01h, Bit 0) to
function as either a lock indicator for the internal PLL or as a
clock running at the input data rate. When Pin 8 is used as a
clock output (DATACLK), its frequency is equal to that of
CLKIN. Data at the input ports is latched into the AD9773 on
the rising edge of the CLKIN. Figure 52 shows the delay, t
inherent between the rising edge of CLKIN and the rising edge
of DATACLK, as well as the setup and hold requirements for
the data at Ports 1 and 2. The setup and hold times given in
Figure 52 are the input data transitions with respect to CLKIN.
Note that in two-port mode (PLL enabled or disabled), the data
rate at the interpolation filter inputs is the same as the input
data rate at Ports 1 and 2.
The DAC output sample rate in two-port mode is equal to the
clock input rate multiplied by the interpolation rate. If zero
stuffing is used, another factor of 2 must be included to
calculate the DAC sample rate.
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