AD9952/PCB Analog Devices Inc, AD9952/PCB Datasheet - Page 8

• Manufacturer Part Number: AD9952/PCB
• Description: BOARD EVAL FOR AD9952
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r
• Type: DDS (Direct Digital Synthesis)r

Specifications of AD9952/PCB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD9952

AD9952
Pin No.
23
24
28
30
31
35
36
37
38
39
40
41
43
44
45
46
Paddle
Mnemonic
DACBP
DAC_R
COMP_OUT
COMP_IN
COMP_IN
PWRDWNCTL
RESET
IOSYNC
SDO
CS
SCLK
SDIO
DVDD_I/O
SYNC_IN
SYNC_CLK
OSK
Exposed Paddle
SET
I/O
I
I
O
I
I
I
I
I
O
I
I
I/O
I
I
O
I
I
Description
DAC Biasline Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.
A resistor (3.92 kΩ nominal) connected from AGND to DAC_R
for the DAC.
Comparator Output.
Comparator Input.
Comparator Complementary Input.
Input Pin Used as an External Power-Down Control. See Table 7 for additional information.
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9952 to the initial state,
as described in the I/O port register map (see Table 5).
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is
returned low. If unused, ground this pin; do not allow this pin to float.
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When
operated as a 2-wire serial port, this pin is unused and can be left unconnected.
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.
This pin functions as the serial data clock for I/O operations.
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.
Digital Power Supply. For I/O cells only, 3.3 V.
Input signal used to synchronize multiple AD9952s. This input is connected to the SYNC_CLK
output of a master AD9952.
Clock output pin that serves as a synchronizer for external hardware.
Input pin used to control the direction of the shaped on-off keying function when programmed
for operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin
should be tied to DGND.
The exposed paddle on the bottom of the package is a ground connection for the DAC and must
be attached to AGND in any board layout. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or
3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only be powered to 1.8 V.
Rev. B | Page 8 of 28
SET
establishes the reference current