HSC-ADC-EVALA-SC Analog Devices Inc, HSC-ADC-EVALA-SC Datasheet
HSC-ADC-EVALA-SC
Specifications of HSC-ADC-EVALA-SC
Related parts for HSC-ADC-EVALA-SC
HSC-ADC-EVALA-SC Summary of contents
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... PC. Two versions of the FIFO are available. The HSC-ADC-EVALA used with dual ADCs and converters with demultiplexed digital outputs. The HSC-ADC-EVALA-SC evaluation board is used with single-channel ADCs. See Table 1, to choose the FIFO appropriate for your high speed ADC evaluation board. ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TABLE OF CONTENTS FIFO Evaluation Board Quick Start............................................... 4 Requirements ................................................................................ 4 Quick Start Steps ...................................................................... 4 Virtual Evaluation Board Quick Start With ADIsimADC.......... 5 Requirements ................................................................................ 5 Quick Start Steps ...................................................................... 5 FIFO 4 Data Capture Board ............................................................ 6 FIFO 4 Supported ADC Evaluation Boards.............................. 6 Terminology ...................................................................................... 8 Single Tone FFT............................................................................ 8 Two-Tone FFT .............................................................................. 9 Theory of Operation ...................................................................... 10 Clocking Description................................................................. 10 Clocking with Interleaved Data ...
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... Layer 4—Secondary Side............................................................40 ESD Caution ................................................................................40 Bill of Materials................................................................................41 Appendix: Sampling and FFT Fundamentals..............................43 Coherent Sampling .....................................................................43 REVISION HISTORY 5/04—Revision 0: Initial Version HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Windowing Functions................................................................43 FFT Calculations.........................................................................43 Ordering Guide ...........................................................................44 Rev Page ...
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... Connect the FIFO evaluation board to the ADC evaluation board adapter is required, insert the adapter between the ADC evaluation board and the FIFO board. If using the HSC-ADC-EVALA-SC model, connect the evaluation board to the bottom half of the 80-pin connector (closest to the installed IDT FIFO chip). ...
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... Stop button. Click Model to select and configure which converter will be modeled. This places a small form in the workspace where you can select and configure how the model will behave. HSC-ADC-EVALA-SC/HSC-ADC-EVALA- the ADC Modeling form, select the Device tab and … ...
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... The evaluation boards in Table 1 can be used with the high speed ADC FIFO Evaluation Kit between the ADC evaluation board connector and the FIFO connector adapter is needed, send an email to highspeed.converters@analog.com with the part number of the adapter and a mailing address. Table 1 HSC-ADC-EVALA-DC: and HSC-ADC-EVALA-SC Compatible Evaluation Boards Evaluation Board Model Description of ADC AD6640ST/PCB ...
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... The AD6640 evaluation board has a 40-pin output connector that should be left (MSB) justified when connected to the 50-pin AD664x FIFO adapter. 4 The AD9281 and AD9201 have a single output bus 5 The High Speed ADC FIFO Evaluation Kit can be used to evaluate two channels of the AD9289 at a time. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC FIFO Board Version ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TERMINOLOGY SINGLE TONE FFT Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc reported in dBc. Signal-to-Noise Ratio Full Scale (SNRFS) The ratio of the rms signal amplitude related to full scale (0 dB) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc ...
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... The resulting rms third order distortion value reported by the mixing of two analog input signals. The peak spurious component is considered an IMD product reported in dBc. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Two-Tone, Worst Other Spur (WoSpur) The resulting rms distortion value, reported by the mixing of two analog input signals that is not related to the second or third order distortion products ...
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... IDT. The system can acquire digital data at speeds up to 133 MSPS and data record lengths using the HSC-ADC-EVALA-SC FIFO evaluation kit. The HSC-ADC- EVALA-DC, which has two FIFO chips, is available to evaluate dual ADCs or demultiplexed data from ADCs sampling faster than 133 MSPS ...
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... To specify a directory different than the default to store the configuration file, enter a new location in the Default Data Directory dialog box, and click OK. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Step 1 2. Choose Config > FFT from the pull-down menus or right- click any of the analysis buttons to open the FFT Configuration screen ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC board. Channel B corresponds to Channel 2 on the FIFO schematics and the top FIFO on the evaluation board (closest to the Analog Devices logo). See the Jumpers section for more information. Configuring FFT— Defining Available Options Samples: Choose the number of samples taken to calculate an FFT ...
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... If a single ADC is being evaluated, check only Channel A and the appropriate bits under Channel dual ADC is being evaluated, check Channel A and Channel B on the Channel Select screen. (Config > Channel Select). HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Step 4 If evaluating a demultiplexed ADC Config > Channel Select, opening the Channel Select pop-up menu, and check the Interleaved Data box ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC evaluation board. Channel B corresponds to Channel 2 on the FIFO schematics and the top FIFO (U101) on the evaluation board (closest to the Analog Devices logo). See the Jumpers section for more information. Click OK. (For more information about the channel selection process, see the Troubleshooting section ...
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... Make any other adjustments necessary. If you have questions, see the Configuring an Evaluation Board. Click OK when finished. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 2. From the menu, select Config > Buffer. From the drop down list, select Model. Then click OK. In effect, the model functions in place of the ADC and data capture hardware ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 5. From the file browser, select the model of interest. When the model is selected, information about that device is filled in on the ADC Modeling form. Note that the amount of jitter, assumed at the time of characterization, automatically inserts in the External Jitter box on the Input tab. The model also returns a default Output Mode which is defined either as Offset Binary or Twos Complement ...
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... DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only) HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Encode: ADC clock rate (MSPS), set under Config > FFT. Analog: Calculated analog input frequency (MHz sampling applications, the analog input is calculated back to the first Nyquist zone. Note that the encode rate must be set properly in the Config > ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TWO TONE This function displays a reconstruction of the captured data in the frequency domain to analyze dual-tone analog inputs. Several values are listed to the left of the signal, including AVCC: Analog voltage level, set under Config > Power Supply (for display purposes only) DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only) Encode: ADC clock rate (MSPS), set under Config > ...
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... Data Format: Select the format of the ADC output data. Justification: Normally, the data exported from ADC Analyzer is MSB_Justified. When importing data, be sure to select the proper justification. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Encode Frequency (MHz): Enter the sampling clock rate used. ASCII Text File to Import: Click the Browse… button to search for the file. ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Figure 11. Import .csv file using MS Excel Parameters, such as Device, Device Number, Analog Frequency, Encode Frequency, Average (value), (number of) Bits, Max (value), Min (value), Range (of values), (amount of) Samples, AVCC, DVCC, XMaxTime, XMinTime, YMaxTime, YMinTime, Date, Time, Device Temperature, and Comments are included at the top of the file ...
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... ADC Modeling form under the Input tab, and must be set prior to selecting this option. Figure 16. Amplitude Sweep Mode Options HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Start Amplitude (dB): This sets the starting level of the amplitude sweep. This is relative to the dc fullscale of the converter. This number should always be lower than the stop amplitude ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Datalog to Screen: Selecting this check box causes graphs of each of the selected plots to be displayed on the screen after completion of the sweep. Datalog Plots to File: Selection of this check box causes each bitmap plot to be written to the default data directory. Datalog Plots to Printer: Selection of this check box causes each bitmap plot to be sent to the printer ...
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... Use the Analyze > Bus Check option to ensure all data bits are switching. See Figure 19 for an example of the AD6645, 14-bit single channel ADC. Note: The left-most bit is the MSB. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 9. Use the ADC data sheet to ensure all jumper connections are set appropriately on the ADC evaluation board. Ensure the ADC power-down option is not active ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Figure 20. Incorrect Setting for Twos Complement FFT NOISE FLOOR HIGHER THAN EXPECTED Figure 21. Example of How Timing Issues Affect the Noise Floor Scenario: The noise floor of the FFT is higher than expected. Note that a higher than expected noise floor on the FFT can often be traced back to timing issues in the clock path ...
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... Perform another FFT. The spur should disappear. MSBs MISSING FROM TIME DOMAIN Figure 25. Incorrect Bit Mask Setting HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Scenario: The two MSBs are missing from the time domain plot evaluating the AD9200, AD9201, AD9280, or AD9281, make sure the appropriate bits are selected under Config > ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC JUMPERS Use the legends below to configure the jumpers. On the FIFO evaluation board, Channel 1 is associated with the bottom IDT FIFO chip, and Channel 2 is associated with the top IDT FIFO chip (closest to the Analog Devices logo). Table 2. Jumper Legend Position ...
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... J402 Position 3 Position 3 J403 Position 1 Position 1 1 Can only be used with a dual channel FIFO board. This is essentially a single channel, but using the opposite channel (top FIFO) rather than the standard default (bottom FIFO). HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Single Channel Dual 1 Settings Channel Settings (Top) ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC FIFO SCHEMATICES AND PCB LAYOUT FIFO CONNECTOR FLOAT 40 39 GND FLOAT FLOAT 36 35 GND GND 34 33 D15 (MSB) GND 32 31 D14 GND 30 29 D13 GND 28 27 D12 GND 26 25 D11 GND 24 23 D10 GND GND GND GND GND GND 12 11 ...
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... CLK Q R521 GND 14 332Ω FF2 1 U505 7 VCC C506 C507 C508 C509 0.1µF 0.1µF 0.1µF 0.1µF HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC R502 100kΩ VCC + C501 CR502 1µF VAL VCC + C502 C503 2.2µF 0.1µF 1 CLKOUT RCLK 32 IFCLK EF1 4 RDY0/*SLRD ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC PCB SCHEMATIC (Continued) VCC C201 C202 C203 C204 C205 C206 C207 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF OPTION TO USE EXTRA BITS ON FIFO J201 D2_17 1 2 J204 J205 J202 D2_16 DUT_CLK2 J203 1 36 ...
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... D1_6 16 15 D1_5 14 13 D1_4 12 11 D1_3 10 9 D1_2 8 7 D1_1 6 5 D1_0 4 3 J107 CTRL_B J106 CTRL_A 1 2 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC E101 VCC WEN1 1 E102 WEN 2 SEN 3 DNC 4 VCC C108 5 0.1µF DNC GND D1_17 8 D17 9 VCC D1_16 10 D16 11 D15 12 D14 ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC PCB SCHEMATIC (Continued) POPULATE WITH PIN SOCKET E302 E301 VCC VCC R301 R303 DNP 331Ω C301 C302 0.1µF 0.1µF EXT_CLK1 J301 R304 331Ω C303 R302 0.1µF DNP J303 1 2 VCC VCC 3 4 HEADER J4 R305 R307 DNP 331Ω ...
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... PCB SCHEMATIC (Continued) VCC R402 DNP R401 WENS 20kΩ 7 C401 R403 0.001µF U401 DNP MC100EPT22 WRT_CLK1 U401 MC100EPT22 J403 4 1 R407 162Ω WRT_CLK2 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC R404 R405 R406 VCC 162Ω 162Ω 130Ω VCC VBB CLK0 Q0 CLK ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC PCB SCHEMATIC (Continued D1_8 DC8 2 15 D1_9 DC9 3 14 D1_10 DC10 4 13 D1_11 DC11 5 12 D1_12 DC12 6 11 D1_13 DC13 7 10 D1_14 DC14 8 9 D1_15 DC15 R601 1 16 D1_0 DC0 2 15 D1_1 DC1 3 14 D1_2 DC2 4 13 D1_3 DC3 5 12 ...
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... ASSEMBLY—PRIMARY SIDE HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Figure 34. Assembly—Primary Side Rev Page ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC ASSEMBLY—SECONDARY SIDE Figure 35. Assembly—Secondary Side Rev Page ...
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... LAYER 1— PRIMARY SIDE HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Figure 36. Layer 1—Primary Side Rev Page ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC LAYER 2—GROUND PLANE Figure 37. Layer 2—Ground Plane Rev Page ...
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... LAYER 3—POWER PLANE HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Figure 38. Layer 3—Power Plane Rev Page ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC LAYER 4—SECONDARY SIDE ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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... R404–405, R407–408 R410–411, R413–414 R406, R409, R412, R415 R501, R524 R502 R503 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Description Package Capacitor 0805 Capacitor 20% 1206 Capacitor 10% 6032 Capacitor 20% 0805 Capacitor 20% 3216 Capacitor, 20% 6032 Capacitor 0805 LED 0603 Diode, 100 V SOD-123 2-Pin Jumper Header ...
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... HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Quantity Reference SC DC Item Designation R504–507, R510–515, R520 R525–526 R508–509 R516–517 R521–522 R523 R603–604 R312, R315 R301–302, R305–306 R402–403 R601–602 RZ605 U101, U201 U301 U302 U401 U402 U403 U501 ...
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... M M where 0.35875 a1 = 0.48829 a2 = 0.14128 a3 = 0.01168 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC The weighting function for a Hanning window is: where: FFT CALCULATIONS Whether a system is coherent or a windowing function has been applied, the resulting data will be processed via a discrete fourier analysis that translates the discrete time-domain samples into the frequency domain. Because in practice ...
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... If an adapter is needed, send an email to highspeed.converters@analog.com 2 Required for Revision C of AD6644 and AD6645 evaluation boards. Revision D and greater are directly compatible with e HSC-ADC-EVALA-SC evaluation board © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...