AD1836A-DBRD Analog Devices Inc, AD1836A-DBRD Datasheet
AD1836A-DBRD
Specifications of AD1836A-DBRD
Related parts for AD1836A-DBRD
AD1836A-DBRD Summary of contents
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... An SPI® port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1836A operates from supply, with master clock provision for a separate output supply to interface with low voltage external circuitry. The AD1836A is available in a 52-lead 2 S MQFP (PQFP) package. FUNCTIONAL BLOCK DIAGRAM ...
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... AD1836A TABLE OF CONTENTS AD1836A—Specifications ............................................................... 3 Absolute Maximum Ratings............................................................ 8 Pin Configuration And Pin Functional Descriptions.................. 9 Functional Overview...................................................................... 11 ADCs............................................................................................ 11 DACs ............................................................................................ 11 Clock Signals ............................................................................... 11 Reset and Power-Down ............................................................. 12 REVISION HISTORY Revision 0: Initial Version Serial Control Port ..................................................................... 12 Power Supply and Voltage Reference....................................... 13 Serial Data Ports—Data Format............................................... 13 SPI Control Registers ...
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... Measurement Bandwidth Word Width Load Capacitance (Digital Output) Load Impedance (Digital Output) Input Voltage HI Input Voltage LO Rating 5 V 25°C 12.288 MHz (48 kHz f , 256 × 1.000 kHz, 0 dBFS (Full Scale) 48 kHz kHz 24 Bits 100 pF 2.5 kΩ 2.4 V 0.8 V Rev Page AD1836A Mode) S ...
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... Input Capacitance Common-Mode Input Volts Dynamic Range ( kHz, –60 dB Input) No Filter (RMS), AD1836AAS With A-Weighted Filter (RMS), AD1836AAS No Filter (RMS), AD1836ACS With A-Weighted Filter (RMS), AD1836ACS Total Harmonic Distortion + Noise (0 dBFS) Full-Scale Output Voltage (Differential) Gain Error Interchannel Gain Mismatch Offset Error ...
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... Typ 25 –40 –40 –65 Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Rev Page AD1836A Typ Max Unit V 0 µA 10 µ Min Typ Max 4 ...
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... AD1836A Table 7. Timing Specifications Parameter MASTER CLOCK AND RESET SPI PORT DAC SERIAL PORT (Normal Modes) DAC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) ADC SERIAL PORT (Normal Modes) ADC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) ADC SERIAL PORT ...
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... From MCLK Rising, 512 × AUXLRCLK Skew From AUXBCLK Falling XLS t AUXBCLK High XBH t AUXBCLK Low XBL f AUXBCLK Frequency XB t AUXLRCLK Setup To AUXBCLK Rising DLS t AUXLRCLK Hold From AUXBCLK Rising DLH Rev Page AD1836A Min Max Unit Mode Mode S – × ...
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... AD1836A ABSOLUTE MAXIMUM RATINGS Table 8. AD1836A Absolute Maximum Ratings Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied ...
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... ADC2 Right Input 1 (MUX/PGA Mode)/Right Positive Input (PGA Differential Mode). ADC2 Right Negative Input (Direct Mode)/ADC2 Right Decoupling Capacitor (MUX/PGA and PGA Differential Mode). Rev Page DGND 38 DSDATA1 DBCLK 37 36 DLRCLK 35 OUTRP3 OUTRN3 34 33 OUTRP2 32 OUTRN2 31 OUTRP1 30 OUTRN1 29 AGND 28 AGND 27 ADC2INRP/CAPR2 AD1836A ...
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... AD1836A Pin No. In/Out Mnemonic 27 I ADC2INRP/CAPR2 28 I AGND 29 I AGND 30 O OUTRN1 31 O OUTRP1 32 O OUTRN2 33 O OUTRP2 34 O OUTRN3 35 O OUTRP3 36 I/O DLRCLK 37 I/O DBCLK 38 I DSDATA1 39 I DGND 40 I DVDD 41 I DSDATA2 42 I DSDATA3 43 O ABCLK 44 O ALRCLK 45 I MCLK ...
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... AD1836A is then switched to 96 kHz operation (via writing to the SPI port), the frequency of the master clock should remain at 12.288 MHz (which is now 128 × f The internal clock used in the AD1836A is 512 × f mode) or 256 × f (96 kHz mode). A clock doubler is used to ...
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... Reset will power down the chip and set the control registers to their default settings. After reset is de-asserted, an initialization routine will run inside the AD1836A to clear all memories to zero. This initialization lasts for approximately 4500 MCLKs. The power-down bit in the DAC Control Register 1 and ADC Control Register 1 will power down the respective digital section ...
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... A special “auxiliary mode” is provided to allow two external stereo ADCs and one external stereo DAC to be interfaced with the AD1836A to provide 8 in/8 out operation. In addition, this mode supports glueless interface to a single SHARC DSP serial port, allowing a SHARC DSP to access all eight channels of analog I/O. In this special mode, many pins are redefined ...
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... AD1836A LRCLK LEFT CHANNEL BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK MSB SDATA LRCLK BCLK SDATA MSB NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL 2. LRCLK NORMALLY OPERATES BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE ...
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... Figure 8. DAC Packed Mode 256 Rev Page SLOT 3 SLOT 4 RIGHT 0 RIGHT 1 LRCLK BCLK DATA SLOT 5 SLOT 6 SLOT 7 SLOT 8 RIGHT 0 RIGHT 1 LRCLK BCLK DATA SLOT 4 SLOT 5 SLOT 6 RIGHT 0 RIGHT 1 RIGHT 2 LRCLK BCLK DATA SLOT 4 SLOT 5 SLOT 6 RIGHT 0 RIGHT 1 RIGHT 2 LRCLK BCLK DATA AD1836A ...
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... AD1836A FSTDM BCLK TDM MSB TDM ASDATA1 1ST CH TDM (OUT) INTERNAL ASDATA1 ADC L0 32 MSB TDM DSDATA1 1ST CH TDM (IN) INTERNAL DSDATA1 DAC L0 32 AUX 2 LRCLK I S (FROM AUX ADC NO. 1) AUX 2 BCLK I S (FROM AUX ADC NO. 1) AAUXDATA1 (IN) (FROM AUX ADC NO. 1) AAUXDATA2 (IN) (FROM AUX ADC NO ...
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... RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN) ASDATA1 ALRCLK ABCLK DSDATA1 DBCLK/AUXBCLK (64f ) S ASDATA2/DAUXDATA AD1836A MASTER SHARC IS ALWAYS SHARC RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN) ASDATA1 ALRCLK ABCLK DSDATA1 DBCLK/AUXBCLK (64f ) S ASDATA2/DAUXDATA AD1836A SLAVE Rev Page AD1836A LRCLK BCLK DAC DATA MCLK LRCLK BCLK DAC DATA MCLK ...
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... AD1836A Table 11. Pin Function Changes in AUX Mode 2 2 Pin Name (I S/AUX Mode Mode 2 ASDATA1( Data Out, Internal ADC1 ASDATA2(O)/DAUXDATA( Data Out, Internal ADC2 2 DSDATA1( Data In, Internal DAC1 2 DSDATA2(I)/AAUXDATA( Data In, Internal DAC2 2 DSDATA3(I)/AAUXDATA2( Data In, Internal DAC3 ALRCLK(O) LRCLK for Internal ADC1, ADC2 ...
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... Bits 010 = DSP Bits 011 = Reserved 100 = Packed Mode 256 101 = Packed Mode 128 110 = Reserved 111 = Reserved Rev Page AD1836A Data Field 9:0 10 Bits Function Bits 9:0 DAC Control 1 DAC Control 2 DAC1L Volume DAC1R Volume DAC2L Volume DAC2R Volume ...
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... AD1836A Table 15. DAC Control Register 2 Address RD/WR Reserved 15, 14 0001 0 00000 Table 16. DAC Volume Registers Address RD/WR 15, 14, 13 0010: DAC1L 0 0011: DAC1R 0100: DAC2L 0101: DAC2R 0110: DAC3L 0111: DAC3R Table 17. ADC Control Register 1 Address RD/WR Reserved 15, 14, 13 10, 9 1100 ...
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... Min Rev Page Left Right MUX/PGA Left MUX MUX/PGA Enable I/P Select Enable Direct Direct 1 = MUX/PGA MUX/PGA 4 Fixed Bits 3:0 0000 The 4 LSBs are always zero. AD1836A Right MUX I/P Select I I/P 1 ...
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... LEFT + V REF LEFT 250Ω – REF PGA CAP2L C2 1nF SELECT INPUT NO 1111 Figure 13. Single-Ended MUX/PGA Mode AD1836A CAP1L C1 1nF – INPUT + V REF + – INPUT PGA CAP2L C2 1nF NOTE ADC2 DIFFERENTIAL PGA INPUT MODE—LEFT CHANNEL ONLY SHOWN. ...
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... Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE AD1836A Products Temperature Package AD1836AAS –40°C to +85°C Ambient AD1836AASRL – ...
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... AD1836A NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03800–0–8/03(0) Rev Page ...