AD9515/PCB Analog Devices Inc, AD9515/PCB Datasheet - Page 21

• Manufacturer Part Number: AD9515/PCB
• Description: BOARD EVAL CLOCK 2CHAN 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9515/PCB

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 13. S5, S6, and S7—OUT1
S5
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
S6
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
S7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
1
OUT1
Divide (Duty Cycle
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
7 (43%)
8 (50%)
9 (44%)
10 (50%)
11 (45%)
12 (50%)
OUT1 OFF
14 (50%)
15 (47%)
16 (50%)
17 (47%)
18 (50%)
19 (47%)
20 (50%)
21 (48%)
22 (50%)
23 (48%)
24 (50%)
25 (48%)
26 (50%)
27 (48%)
28 (50%)
29 (48%)
30 (50%)
31 (48%)
32 (50%)
2 (50%)
4 (50%)
4 (50%)
4 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
1
)
OUT1
Phase
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
3
1
2
3
4
5
6
7
1
2
3
4
5
6
Rev. 0 | Page 21 of 28
S5
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
Table 14. S8—OUT0/OUT1 Phase (Delay) Select
(Used with S9 to S10)
S8
0
1/3
2/3
1
Table 15. S9 and S10
S9
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
A phase > 0 in Table 12 or overrides the phase in Table 15.
Duty cycle is the clock signal high time divided by the total period.
S10
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
S6
0
1/3
1/3
2/3
2/3
1
1
0
0
1/3
1/3
2/3
2/3
1
1
OUT0
No Phase
Phase
No Phase
Phase (Start High)
OUT0 or OUT1 Phase
(Depends on S8)
Phase
0
1
2
3
4
7
8
11
12
13
14
15
5
6
9
10
S7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUT1
Divide (Duty Cycle
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
32 (50%)
32 (50%)
32 (50%)
32 (50%)
32 (50%)
Do not use
OUT1 (Delay if S0 ≠ 0)
Phase (Delay)
No Phase
Phase (Delay) (Start High)
No Phase
OUT1 Delay (S0 ≠ 0)
(Depends on S8)
Fine Delay
0
1/16
1/8
3/16
1/4
5/16
3/8
7/16
1/2
9/16
5/8
11/16
3/4
13/16
7/8
15/16
1
)
AD9515
OUT1
Phase
7
8
9
10
11
12
13
14
15
1
2
3
4
5