AD9518-3/PCBZ Analog Devices Inc, AD9518-3/PCBZ Datasheet - Page 44
AD9518-3/PCBZ
Manufacturer Part Number
AD9518-3/PCBZ
Description
BOARD EVAL FOR AD9518-3
Manufacturer
Analog Devices Inc
Specifications of AD9518-3/PCBZ
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
AD9518-3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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AD9518-3
Table 40. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
DS
DH
CLK
S
C
HI
LO
DV
SCLK
SDIO
CS
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a Logic High state
Minimum period that SCLK should be in a Logic Low state
SCLK to valid SDIO and SDO (see Figure 47)
t
t
DS
S
BIT N
t
HI
t
DH
Figure 49. Serial Control Port Timing—Write
t
CLK
Rev. 0 | Page 44 of 64
t
LO
BIT N + 1
t
C
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