M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 19

KIT EVAL FOR M5249 W/ETHERNET

M5249C3

Manufacturer Part Number
M5249C3
Description
KIT EVAL FOR M5249 W/ETHERNET
Manufacturer
Freescale Semiconductor
Series
ColdFire®r
Type
Microprocessorr
Datasheets

Specifications of M5249C3

Contents
Module and Misc Hardware
Processor To Be Evaluated
MCF5249
Interface Type
RS-232, Ethernet
For Use With/related Products
MCF5249
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
8.7
As the SCF5249 has a quite complicated slave bus, with the possibility to put DRAM on the bus, put
asynchronous memories on the bus, and to put ISA bus peripherals on the bus, it may become necessary
to introduce a bus buffer on the bus. The SCF5249 has a glueless interface to steer these bus buffers with
2 bus buffer output signals BUFENB1/GPIO57 and BUFENB2/GPIO7.
8.8
There are two I
The I
and peripherals with an I
devices connected to the I
be accomplished with an open-drain output.
8.9
The following signals transfer serial data between the two UART modules and external peripherals.
All serial module signals can be used as gpi or gpo. The GPIO-FUNCTION and GPIO1-FUNCTION
registers must be programmed to determine pin functions of the inputs and outputs. If used as gpo or gpi,
UART functionality is lost.
Freescale Semiconductor
2
C module acts as a quick two-wire, bidirectional serial interface between the SCF5249 processor
Bus Buffer Signals
I
Serial Module Signals
2
C Module Signals
The BUFENB2 signal is only used in the 160 MAPBGA package.
2
I
2
C interfaces on this device.
I
c Module Signal
I
2
2
C Serial Clock
C Serial Data
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
2
2
C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When
C bus drive the bus, they will either drive logic-0 or high-impedance. This can
Table 6. I
The SCL/QPSICLK and SCL2/GPIO3 bidirectional signals are
the clock signal for first and second I
I
mode; all I
timing.
Signals are multiplexed
Function select is done via PLLCR register.
The SDA/QSPI_DIN and SDA2/GPIO55 bidirectional signals
are the data input/output for the first and second serial I
interface.
Signals are multiplexed
Function select is done via PLLCR register.
2
C module controls this signal when the bus is in master
2
C Module Signals
NOTE
2
C devices drive this signal to synchronize I
Description
2
C module operation. The
Signal Descriptions
2
C
2
C
19

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