EDK2215 Renesas Electronics America, EDK2215 Datasheet - Page 8

• Manufacturer Part Number: EDK2215
• Description: DEV EVALUATION KIT H8S/2215
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: Microcontrollerr

Specifications of EDK2215

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8S/2215
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.4. M
Table 4-4 illustrates the EDK memory map for mode 6.
4.5. SRAM A
4.6.
The EDK has four red LEDs. The function of each LED is clearly marked on the silk screen of the PCB. Please refer to the
board layout diagram for position information (Section 3).
When the board is connected to a power source the Power (PWR) led will illuminate. The Boot mode indication LED will
illuminate when the microcontroller has been placed into Boot mode. Please see section 5.5 for more details of this function.
There are two LEDs dedicated for user control these are marked USR1 and USR2. Each LED will illuminate when the port
pin is in a logical high state.
External access timing is defined by several registers, allowing different types of devices to be addressed. The
registers for the selection of wait states and signal extensions are given below with recommended values for the
EDK.
ABWCR
WCR
PADDR
PBDDR
PCDDR
PFDDR
PGDDR
Please refer to the hardware manual of the microcontroller for further information on these register settings.
LED
EMORY
Register
S
M
CCESS TIMING
AP
H’0000 0000
H’0003 FFFF
H’0040 0000
H’0043 FFFF
H’0044 0000
H’00BFFFFF
H’00C00000
H’00DFFFFF
H’00E00000
H’00FF8FFF
H’00FF9000
H’00FFAFFF
H’00FF B000
H’00FF EFBF
H’00FF EFC0
H’00FF F7FF
H’00FF F800
H’00FF FF3F
H’00FF FF40
H’00FF FF5F
H’00FF FF60
H’00FF FFBF
H’00FF FFC0
H’FFFFFFFF
H’FED0
H’FED2
H’FE39
H’FE3A
H’FE3B
H’FE3E
H’FE3F
Address
Section Start
Section End
T
ABLE
0x00
0xFF
0xFF
0x02
0x01
0xFF
0x09
Recommended Setting for
4-4: M
EMORY
EDK
On-Chip ROM
External RAM
External Address Space
On-Chip USB Registers
External Address Space
Reserved
On-Chip RAM
RESERVED
Internal I/O Registers
RESERVED
Internal I/O Registers
On-Chip RAM
M
AP
(D
EFAULT
Section Allocation
M
ODE
8bit R/W access. Bus Width Control Register. All
areas set to 16 bit access
16bit R/W access. Wait State Control Register –
area 2 set to 3 wait states
8bit R/W access. Port A data direction register.
Address Bus (A16)
8bit R/W access. Port B data direction register.
Address Bus (A15:8)
8bit R/W access. Port C data direction register.
Address bus (A7:0)
8bit R/W access. Port F data direction register.
RAM control (HWRn/LWRn)
8bit R/W access. Port G data direction register.
Chip Select 2.
6)
Function
8