HS7727KCI01H Renesas Electronics America, HS7727KCI01H Datasheet - Page 27

• Manufacturer Part Number: HS7727KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7727KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.2.4
1. When JTAG clock (TCK) is used, set the JTAG clock (TCK) frequency to lower than the
2. Set the AUD clock (AUDCK) frequency to 50 MHz or below for PCMCIA and PCI cards. The
2.2.5
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
3. During step execution, a BREAKPOINT is disabled.
4. Conditions set at Break Condition 2 are disabled when an instruction to which a
5. When execution resumes from the address where a BREAKPOINT is specified, single-step
6. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
7. When a BREAKPOINT is set to the cacheable area, the cache block containing the
8. Note on DSP repeat loop:
9. When the [Normal] option is selected in the [Memory area] group box in the [General] page of
frequency of half of the CPU clock.
upper limit of the AUD clock must be lower than the CPU clock and the lower limit must be
the quarter of the CPU clock.
Accordingly, it can be set only to the internal RAM area. However, a BREAKPOINT cannot
be set to the following addresses:
BREAKPOINT has been set is executed. Do not set a BREAKPOINT to an instruction in
which Break Condition 2 is satisfied.
execution is performed at the address before execution resumes. Therefore, realtime operation
cannot be performed.
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
BREAKPOINT address is filled immediately before and after user program execution.
A BREAKPOINT is equal to a branch instruction. In some DSP repeat loops, branch
instructions cannot be set. For these cases, do not set BREAKPOINTs. Refer to the hardware
manual for details.
the [Configuration] dialog box, a BREAKPOINT is set to a physical address or a virtual
address according to the SH7727 MMU status during command input when the VPMAP_SET
command setting is disabled. The ASID value of the SH7727 PTEH register during command
input is used. When VPMAP_SET command setting is enabled, a BREAKPOINT is set to a
physical address into which address translation is made according to the VP_MAP table.
An area other than CS0 to CS6 and the internal RAM
An instruction in which Break Condition 2 is satisfied
A slot instruction of a delayed branch instruction
An area that can be only read by MMU
Notes on Using the JTAG Clock (TCK) and AUD Clock (AUDCK)
Notes on Setting the [Breakpoint] Dialog Box
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