HS7729RKCI02H Renesas Electronics America, HS7729RKCI02H Datasheet - Page 223
HS7729RKCI02H
Manufacturer Part Number
HS7729RKCI02H
Description
ON CHIP DEBUG EMULATOR W/TRACE
Manufacturer
Renesas Electronics America
Datasheets
1.HS7729RKCI02H.pdf
(234 pages)
2.HS7729RKCI02H.pdf
(30 pages)
3.HS7729RKCI02H.pdf
(14 pages)
Specifications of HS7729RKCI02H
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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10. An address (physical address) to which a breakpoint is set is determined when the breakpoint
11. When a breakpoint is set to the cacheable area, the cache block containing the breakpoint
12. Note on DSP repeat loop:
6.5.6
1. Break Condition 2 is disabled during step execution.
2. Break Condition 2 is disabled when an instruction to which a BREAKPOINT has been set is
3.
4.
6.5.7
1. When MMU settings are modified or when a user program is changed after GO command
2. When a completion-type exception occurs during exception branch acquisition, the next
value after setting. When no ASID value is specified, the breakpoint is set to a virtual address
corresponding to the ASID value at command input.
is set. Accordingly, even if the VP_MAP table is modified after breakpoint setting, the
breakpoint address remains unchanged. When a breakpoint is satisfied with the modified
address in the VP_MAP table, the cause of termination displayed in the status bar and the
[System Status] window is ILLEGAL INSTRUCTION, not BREAKPOINT.
executed. Accordingly, do not set a BREAKPOINT to an instruction which satisfies Break
Condition 2.
completion before trace display, the displayed mnemonics or operand may not be correct.
address to the address in which an exception occurs is acquired.
address is filled immediately before and after user program execution.
A breakpoint is equal to a branch instruction. In some DSP repeat loops, branch instructions
cannot be set. For these cases, do not set breakpoints. Refer to the hardware manual for
details.
When a Break Condition is satisfied, emulation may stop after two or more instructions have
been executed.
If a PC break address condition is set to the slot instruction after a delayed branch instruction,
user program execution cannot be terminated before the slot instruction execution; execution
stops before the branch destination instruction.
Notes on Setting the [Break Condition] Dialog Box
Notes on Setting the [Trace] Window
203
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