HS7760KCM02H Renesas Electronics America, HS7760KCM02H Datasheet - Page 266
HS7760KCM02H
Manufacturer Part Number
HS7760KCM02H
Description
ON CHIP DEBUG EMULATOR W/TRACE
Manufacturer
Renesas Electronics America
Datasheets
1.HS7760KCI02H.pdf
(278 pages)
2.HS7760KCI02H.pdf
(50 pages)
3.HS7760KCI02H.pdf
(13 pages)
Specifications of HS7760KCM02H
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 7.5 Performance Count Conditions (cont)
Event
Pipeline freeze cycle due
to branch instruction or
exception
Examples:
To set the elapsed-time measurement in the <mode> item and count using the ratio of the CPU
operating clock to the bus clock in the <clock> item in channel 1:
To set the elapsed-time measurement in the <mode> item, count using the ratio of the CPU
operating clock to the bus clock in the <clock> item, and set the measurement start and end at the
satisfaction of Break Condition 4:
240
ps channel 1 mode tm clock bus (RET)
ps channel 2 mode tm clock bus range u (RET)
Count Condition
Counts only one cycle at branch instruction
execution except when the delay slot instruction is
executed with one-cycle delay. One instruction is
executed in one cycle, which is similar to the
branch count. When the instruction in the branch
destination does not exist in the instruction cache,
the delay after the second cycle is counted by the
ECF. In the PFB, all branch instructions can be
counted.
PFB
Target Mode
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