CWX-OSK-D500K-DL Freescale Semiconductor, CWX-OSK-D500K-DL Datasheet - Page 2

• Manufacturer Part Number: CWX-OSK-D500K-DL
• Description: SOFTWARE DIST LICENSE
• Manufacturer: Freescale Semiconductor
• Type: CodeWarrior™r

Specifications of CWX-OSK-D500K-DL

• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: -

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© Freescale Semiconductor, Inc. 2005. © Metrowerks Corp. 2005. Metrowerks is a Freescale company.
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950-00048
REV B
Context switch between tasks (ActiveTask)
Terminate task with return to background task
Context switch from ISR (ActiveTask)
OSEKturbo Performance
Information
OSEK Real Time Operating System
Freescale OSEKturbo OS Products
OSEKturbo releases exist for all OS (BCC1,
ECC1, BCC2, ECC2) and COM (CCCA and
CCCB) conformance classes.
Supported Processors (check with your local
Freescale sales office for latest list)
> Freescale 68HC08
> Freescale 68HC(S)12
> Freescale MPC5xx
> Freescale MPC5200
> Freescale DSP56800E
> Freescale S12X
> Freescale MPC55xx
> Freescale MAC7100
Technical Enhancements
> Timescale feature that enables cyclic task
activations based on efficient alarms
OSEKturbo Performance Information
Context switch timings:
•
Measurements done with Timer capture (MPC555: TB, time base
register; HCS12DP256: TCNT, timer count register)
ActivateTask is called
called task executed
CONTEXT SWITCH
First instruction in
BETWEEN TASKS
40MHz; BCC1
MPC555
1.7µs
2.1µs
0.9µs
> OSEKturbo highly optimized for speed and
> ORTI (OSEK Runtime Interface) for kernel
> Enhanced OSEK Builder for OIL
> Multiple scheduling policies
> Event control for task synchronization
> Resource management based on OSEK
> Counter management
> Efficient alarm management
> Optimal stack methods
> Stack monitoring
> Fast links for accessing system data
> Automatic exclusion of unused system
> Specific hardware features such as
memory on each target
aware debugging
configuration
priority ceiling protocol
structures
services
memory bank switching and use of low
HCS12DP256
8MHz; BCC1
Call Terminate Task
12.5µs
14.9µs
6.6µs
instruction in previous task
Ready to call first
TERMINATE
TASK TIME
Typical Memory Requirements:
•
•
Tasks activated consecutively, ISR that activates tasks as well
19 tasks, 3 ISRs, STANDARD status
Total OS ROM
Total OS RAM
OS data
OS code
> Full internal OSEK communication for inter
> Task management for activation and
> Interrupt management
> Error handling
Benchmark configuration:
> BCC1 with one task per priority
> Pre-emptive Scheduling
> No multiple activations
> 10 basic tasks + 1 initialization task
> 10 alarms with task activations
> 1 16-bit (1 ms)
> 1 ISR (in addition to system timer)
> No messages, no resources
> Standard status, debug level zero
> No hooks
power modes, interrupt handler and
Floating Point registers
process communication
termination of tasks
2304 bytes
2196 bytes
466 bytes
108 bytes
MPC555
TASK 2
TASK 1
HCS12DP256
776 bytes
716 bytes
60 bytes
90 bytes