74aup1g80 NXP Semiconductors, 74aup1g80 Datasheet

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74aup1g80

Manufacturer Part Number
74aup1g80
Description
74aup1g80 Low-power D-type Flip-flop; Positive-edge Trigger
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features
The 74AUP1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial Power-down applications using I
The I
the device when it is powered down.
The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information
on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock
transition for predictable operation.
I
I
I
I
I
I
I
I
I
I
I
CC
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
Rev. 01 — 20 October 2006
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
N
N
N
N
N
N
N
N
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114-D exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101-C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
.

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74aup1g80 Summary of contents

Page 1

... OFF the device when it is powered down. The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation ...

Page 2

... Temperature range Name 74AUP1G80GW +125 C 74AUP1G80GM +125 C 74AUP1G80GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G80GW 74AUP1G80GM 74AUP1G80GF 5. Functional diagram mna649 Fig 1. Logic symbol CP D Fig 3. Logic diagram 74AUP1G80_1 Product data sheet Low-power D-type flip-flop; positive-edge trigger ...

Page 3

... D 2 clock pulse input CP 3 ground ( data output Q 5 not connected 6 supply voltage Rev. 01 — 20 October 2006 74AUP1G80 74AUP1G80 n.c. GND 001aaf507 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) Output ...

Page 4

... V O Active mode and Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode and Power-down mode Rev. 01 — 20 October 2006 74AUP1G80 Min Max Unit 0.5 +4 [1] 0.5 +4 [1] 0.5 +4.6 ...

Page 5

... 3 0 GND GND GND Rev. 01 — 20 October 2006 74AUP1G80 Min Typ Max 0 0.75 V ...

Page 6

... GND Rev. 01 — 20 October 2006 74AUP1G80 Min Typ Max 0 ...

Page 7

... GND GND. CC Rev. 01 — 20 October 2006 74AUP1G80 Min Typ Max 0 ...

Page 8

... [2] Figure 1.3 V 3 1.6 V 2 1.95 V 2 2.7 V 1 3.6 V 1.8 Figure Rev. 01 — 20 October 2006 74AUP1G80 +125 C [1] Max Min Max (85 C) (85 C) (125 C) 20 6.0 12.9 2.6 14.3 4.2 7.6 2.0 8.9 3.4 5.9 1.6 7.0 2.6 4.3 1.2 5.6 2.2 3.6 1.0 4 ...

Page 9

... V to 1.3 V 4 1.6 V 4 1.95 V 3 2.7 V 3 3.6 V 2.9 Figure Figure Rev. 01 — 20 October 2006 74AUP1G80 +125 C [1] Max Min Max (85 C) (85 C) (125 C) 28 7.6 16.7 3.4 18.6 5.3 9.8 2.6 11.5 4.4 7.6 2.3 9.1 3.5 5.7 2.0 6.9 3.1 5.0 1.8 5 ...

Page 10

... where Rev. 01 — 20 October 2006 74AUP1G80 +125 C [1] Max Min Max (85 C) (85 C) (125 C) 1 0.3 - 2.0 - 0.2 - 1.3 - 0.2 - 1.1 - 0.3 - 0.8 - 0.3 - 0 -0.4 - ...

Page 11

... V M GND su(L) 1/f max GND PLH Table 9. Input 0 Rev. 01 — 20 October 2006 74AUP1G80 PHL V M mna652 su(H) t PHL mna653 3 © NXP B.V. 2006. All rights reserved ...

Page 12

... Low-power D-type flip-flop; positive-edge trigger PULSE DUT GENERATOR for measuring propagation delays, setup and hold times and pulse width R L Rev. 01 — 20 October 2006 74AUP1G80 V EXT 001aac521 of the pulse generator EXT ...

Page 13

... 1 scale (1) ( 0.30 0.25 2.25 1.35 0.65 0.15 0.08 1.85 1.15 REFERENCES JEDEC JEITA MO-203 SC-88A Rev. 01 — 20 October 2006 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger detail 2.25 0.46 1.3 0.425 0.3 0.1 2.0 0.21 ...

Page 14

... Low-power D-type flip-flop; positive-edge trigger scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 20 October 2006 74AUP1G80 4 ( EUROPEAN PROJECTION SOT886 ISSUE DATE 04-07-15 04-07-22 © NXP B.V. 2006. All rights reserved ...

Page 15

... Product data sheet Low-power D-type flip-flop; positive-edge trigger scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 01 — 20 October 2006 74AUP1G80 SOT891 2 mm EUROPEAN ISSUE DATE PROJECTION 05-03-11 05-04-06 © NXP B.V. 2006. All rights reserved ...

Page 16

... Revision history Table 12. Revision history Document ID Release date 74AUP1G80_1 20061020 74AUP1G80_1 Product data sheet Low-power D-type flip-flop; positive-edge trigger Data sheet status Change notice Product data sheet - Rev. 01 — 20 October 2006 74AUP1G80 Supersedes - © NXP B.V. 2006. All rights reserved ...

Page 17

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 20 October 2006 74AUP1G80 © NXP B.V. 2006. All rights reserved ...

Page 18

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 20 October 2006 Document identifier: 74AUP1G80_1 ...

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