74lvc1g125gm NXP Semiconductors, 74lvc1g125gm Datasheet

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74lvc1g125gm

Manufacturer Part Number
74lvc1g125gm
Description
74lvc1g125 Bus Buffer/line Driver; 3-state
Manufacturer
NXP Semiconductors
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVC1G125GM
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74lvc1g125gm,115
Manufacturer:
NXP Semiconductors
Quantity:
4 000
1. General description
2. Features
The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (OE). A HIGH-level at pin OE
causes the output to assume a high-impedance OFF-state.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
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74LVC1G125
Bus buffer/line driver; 3-state
Rev. 07 — 30 August 2007
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
ESD protection:
Complies with JEDEC standard:
N
N
N
N
N
24 mA output drive (V
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74lvc1g125gm Summary of contents

Page 1

Bus buffer/line driver; 3-state Rev. 07 — 30 August 2007 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH-level at pin OE ...

Page 2

... Temperature range Name 74LVC1G125GW +125 C 74LVC1G125GV +125 C 74LVC1G125GM +125 C 74LVC1G125GF +125 C 4. Marking Table 2. Marking Type number 74LVC1G125GW 74LVC1G125GV 74LVC1G125GM 74LVC1G125GF 5. Functional diagram mna118 Fig 1. Logic symbol 74LVC1G125_7 Product data sheet Description TSSOP5 plastic thin shrink small outline package; 5 leads; ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC1G125 GND 001aaf198 Fig 4. Pin configuration SOT353-1 and SOT753 6.2 Pin description Table 3. Pin description Symbol Pin SOT353-1/SOT753 GND n. Functional description [1] Table 4. Function table Input ...

Page 4

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current I I OFF-state output current ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay see enable time see disable time see dis ...

Page 8

... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 7. Input A to output Y propagation delay times OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...

Page 9

... NXP Semiconductors Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9. Load circuitry for switching times Table 10 ...

Page 10

... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE ...

Page 11

... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions UNIT 0.100 0.40 1.1 0.26 mm 0.013 0.25 0.9 0.10 OUTLINE VERSION IEC SOT753 Fig 11. Package outline SOT753 74LVC1G125_7 Product data sheet scale 3.1 1.7 3.0 0.6 0.95 2.7 1.3 2.5 0.2 REFERENCES ...

Page 12

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION ...

Page 13

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 13. Package outline SOT891 (XSON6) ...

Page 14

... Document ID Release date 74LVC1G125_7 20070830 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • In current. • Figure 13 “Package outline SOT891 (XSON6)” ...

Page 15

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 16

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 14 Abbreviations ...

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