74LVC4245AD,112 NXP Semiconductors, 74LVC4245AD,112 Datasheet

IC TRANSCVR TRI-ST DL 24SOIC

74LVC4245AD,112

Manufacturer Part Number
74LVC4245AD,112
Description
IC TRANSCVR TRI-ST DL 24SOIC
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC4245AD,112

Logic Function
Translator, 3-State
Number Of Bits
8
Input Type
TTL
Output Type
TTL
Number Of Channels
8
Number Of Outputs/channel
1
Differential - Input:output
No/No
Propagation Delay (max)
8ns
Voltage - Supply
1.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Package / Case
24-SOIC (7.5mm Width)
Supply Voltage
1.5 V ~ 5.5 V
Logic Family
74LVC
Propagation Delay Time
10 ns
Maximum Operating Temperature
125 C
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Logic Type
Standard Transceivers
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1585-5
74LVC4245AD
935260749112
1. General description
2. Features
The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. It is designed to
interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.
The device features an output enable input (pin OE) for easy cascading and a
send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the
buses are effectively isolated.
In suspend mode, when V
other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be
smaller than V
V
I
I
I
I
I
I
I
I
I
I
CCA
74LVC4245A
Octal dual supply translating transceiver; 3-state
Rev. 06 — 18 January 2008
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Wide supply voltage range:
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
Complies with JEDEC standard no. JESD8B/JESD36
ESD protection:
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
N
N
N
N
3 V port (V
5 V port (V
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
V
CCB
, except in suspend mode.
diode
CCB
CCA
(typical 0.7 V).
): 1.5 V to 3.6 V
): 1.5 V to 5.5 V
CCA
CC
is zero, there will be no current flow from one supply to the
= 0 V
Product data sheet

Related parts for 74LVC4245AD,112

74LVC4245AD,112 Summary of contents

Page 1

Octal dual supply translating transceiver; 3-state Rev. 06 — 18 January 2008 1. General description The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions designed ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC4245AD +125 C 74LVC4245ADB +125 C 74LVC4245APW +125 C 74LVC4245ABQ +125 C 4. Functional diagram 22 G3 3EN1 2 3EN2 mna452 Fig 1. IEC Logic symbol 74LVC4245A_6 Product data sheet Octal dual supply translating transceiver; 3-state ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVC4245A V 1 CCA DIR GND 11 GND 12 001aaa349 Fig 3. Pin configuration SO24 and (T)SSOP24 5.2 Pin description Table 2. Pin description Symbol V CCA V CCB GND DIR A[0:7] B[0:7] OE 74LVC4245A_6 Product data sheet Octal dual supply translating transceiver; 3-state ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Functional table Input OE DIR [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol ...

Page 5

... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage V ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply current CC C input capacitance I C input/output capacitance I +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage LOW-level output voltage V ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply current CC [1] All typical values are measured at V [2] For transceivers, the parameter 3.6 V: other inputs at V CCB 5.5 V: other inputs at V CCA 10 ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). V Symbol Parameter Conditions t output skew sk(o) time C power 5 V port An; PD dissipation V = GND capacitance V = 5.0 V CCA outputs enabled outputs disabled 3 V port Bn GND 3.3 V CCB outputs enabled outputs disabled [1] Typical values are measured at T [2] Skew between any two outputs of the same package switching in the same direction ...

Page 9

... NXP Semiconductors CCB CCA CCA V and V are typical output voltage drops that occur with the output load Fig 6. Input (An, Bn) to output (Bn, An) propagation delays OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH CCB CCA CCA 0 CCB 0 CCB V and V are typical output voltage drops that occur with the output load ...

Page 10

... NXP Semiconductors Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 8. Load circuitry for switching times Table 8. Test data Supply voltage V V CCA CCB < 2.7 V < 3 5.5 V ...

Page 11

... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 10. Package outline SOT340-1 (SSOP24) ...

Page 13

... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 15

... Document ID Release date 74LVC4245A_6 20080118 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 16

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history ...

Related keywords