XA-S3 NXP Semiconductors, XA-S3 Datasheet

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XA-S3

Manufacturer Part Number
XA-S3
Description
The XA-S3 device is a member of Philips Semiconductors? XA(eXtended Architecture) family of high performance 16-bitsingle-chip microcontrollers
Manufacturer
NXP Semiconductors
Datasheet
Semiconductors
Preliminary specification
Supersedes data of 2000 Aug 22
hilips
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D,
low voltage (2.7 V–5.5 V), I
16 MB address range
INTEGRATED CIRCUITS
2
C, 2 UARTs,
2000 Dec 01

XA-S3 Summary of contents

Page 1

... XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V address range Preliminary specification Supersedes data of 2000 Aug 22 hilips Semiconductors INTEGRATED CIRCUITS UARTs, 2000 Dec 01 ...

Page 2

... K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range GENERAL DESCRIPTION The XA-S3 device is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-S3 device combines many powerful peripherals on one chip. With its high performance A/D converter, timers/counters, ...

Page 3

... P5.2/AD2 25 P5.3/AD3 2000 Dec PLASTIC LEADED CHIP CARRIER Preliminary specification XA- P2.1/A13D9 59 P2.0/A12D8 58 P0.7/A11D7 57 P0.6/A10D6 56 P0.5/A9D5 P0.4/A8D4 52 P0.3/A7D3 51 P0.2/A6D2 50 RST 49 CLKOUT 48 PSEN 47 ALE/PROG 46 P0.1/A5D1 45 P0 ...

Page 4

... P5.3/AD3 2000 Dec LOW PROFILE PLASTIC QUAD FLAT PACK Preliminary specification XA- P2.1/A13D9 58 P2.0/A12D8 57 P0.7/A11D7 56 P0.6/A10D6 55 P0.5/A9D5 P0.4/A8D4 49 P0.3/A7D3 48 P0 ...

Page 5

... REF– CLKOUT ALE PSEN RSTOUT RST EA/WAIT WRH/ RxD1 TxD1 T2 T2EX RxD0 TxD0 INT0 INT1 T0 T1/BUSW WRL RD 2000 Dec XTAL1 XTAL2 5 Preliminary specification XA-S3 ECI CEX0 CEX1 CEX2 CEX3 CEX4 A20 A21 A/D INPUTS SCL SDA A22 A23 SU00847A ...

Page 6

... BLOCK DIAGRAM XA CPU Core Program Memory Bus 32K Bytes ROM/EPROM Data Bus 1024 Bytes Static RAM Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 2000 Dec 01 SFR bus UART 0 UART Timer 0, 1 Timer 2 Watchdog Timer PCA Input Port/ A/D SU00846 6 Preliminary specification XA-S3 ...

Page 7

... Reset Output: This pin outputs a low whenever the XA-S3 processor is reset for any reason. This includes an external reset via the RST pin, watchdog reset, and the RESET instruction ...

Page 8

... Capture/compare external I/O for PCA module 1. CEX2 (P4.3): Capture/compare external I/O for PCA module 2. CEX3 (P4.4): Capture/compare external I/O for PCA module 3. CEX4 (P4.5): Capture/compare external I/O for PCA module 4. A20 (P4.6): Address bit 20 of the external address bus. A21 (P4.7): Address bit 21 of the external address bus. 8 Preliminary specification XA-S3 ...

Page 9

... CCF4 490 CIDL WDTE – – 48B 48A 491 – ECOM0 CAPP0 CAPN0 492 – ECOM1 CAPP1 CAPN1 9 Preliminary specification XA- serial clock input/output serial data input/output. Reset LSB Value 3F3 3F2 3F1 3F0 ADRES ADMOD ADSST ADINT 00h ...

Page 10

... A17D13 A16D12 39F 39E 39D 39C 433 RD WRL T1 T0 3A7 3A6 3A5 3A4 434 A21 A20 CEX4 CEX3 10 Preliminary specification XA-S3 Reset LSB Value MAT2 TOG2 PWM2 ECCF2 00h MAT3 TOG3 PWM3 ECCF3 00h MAT4 TOG4 PWM4 ECCF4 00h ...

Page 11

... SM0_1 SM1_1 SM2_1 REN_1 32F 32E 32D 32C 425 – – – ERR1 464 465 11 Preliminary specification XA-S3 Reset LSB Value 3AB 3AA 3A9 3A8 AD3 AD2 AD1 AD0 FFh 3B1 3B0 – – A23 A22 FFh Note 5 ...

Page 12

... T2CON); TF1, TF0, IE1, and IE0 (in TCON); and WDTOF (in WDCON). 9. The XA-S3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide . All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte. ...

Page 13

... Data Memory (Directly or Indirectly Addressable, On-Chip 2000 Dec 01 FFFFFh Total Code Memory 8000h 7FFFh 32 kB On-chip Code Memory 0000h SU01219 Figure 1. XA-S3 program memory map FFFFh FFFFh 0400h 0400h 03FFh 03FFh Directly 0040h 0040h Addressed 003Fh 003Fh Data (1 k per ...

Page 14

... FUNCTIONAL DESCRIPTION Details of XA-S3 functions will be described in the following sections. Analog to Digital converter The XA-S3 has an 8-channel, 8-bit A/D converter with 8 sets of result registers, single scan and multiple scan operating modes. The A/D also has a 10-bit conversion mode that provides greater result resolution. The A/D input range is limited The A/D inputs are on Port 5 ...

Page 15

... A/D Timing Configuration Conversion Time Osc. Clocks sec at max. Osc 100 104 116 108 124 128 132 146 136 152 172 176 15 Preliminary specification XA-S3 LSB ADCS2 ADCS1 ADCS0 SU00939 LSB SU00940 Sampling Time p g (Osc. Clocks) 10.81 4 7.6 6 7.2 8 7.2 8 6 ...

Page 16

... A/D timing configuration N+1 N Multiplexer fully charge while the multiplexer switch is closed. Please note that sampling C Figure 4. A/D Input: Equivalent Circuit 16 Preliminary specification XA-S3 Sampling Time p g (Osc. Clocks) 13.21 4 9.2 6 8.64 8 8.7 8 7.2 10 6.2 12 6.8 24 5. ...

Page 17

... K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range A/D Accuracy The XA-S3 A -bit mode is specified with 16 samples averaged in order to factor out on-chip noise application where averaging 16 samples is not practical, the accuracy specifications may be de-rated according to the number of samples 1.50 1 ...

Page 18

... UARTs address range Interface 2 The I C interface on the XA-S3 is identical to the standard byte-style interface found on devices such as the 8xC552 except for the 2 rate selection. The I C interface conforms to the 100 kHz I specification, but may be used at rates up to 400 kHz (non-conforming) ...

Page 19

... NOTES The XA- interface does not conform to the 400kHz I may be used with care where higher rates are required by the application The timer 1 overflow is used to clock the I 2000 Dec 01 2 The I C Status Register, I2STA ...

Page 20

... K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range XA-S3 Timer/Counters The XA-S3 has three general purpose counter/timers, two of which may also be used as baud rate generators for either or both of the UARTs. Timer 0 and 1 These are identical to the standard XA-G3 timer 0 and 1. Timer 2 This is identical to the standard XA-G3 timer 2 ...

Page 21

... CF CR –– CCF4 CCF3 Figure 8. PCA Timer/Counter CF CR –– CCF4 CCF3 CCAPMn.0 ECCFn Figure 9. PCA Interrupt System 21 Preliminary specification XA-S3 TO PCA MODULES OVERFLOW INTERRUPT CL CMOD CPS1 CPS0 ECF (490H) CCON CCF2 CCF1 CCF0 (41AH) SU01304 CCON ...

Page 22

... Dec 01 – – – CPS1 Figure 10. CMOD: PCA Counter Mode Register – CCF4 CCF3 CCF2 Figure 11. CCON: PCA Counter Control Register 22 Preliminary specification XA-S3 Reset Value = 00H CPS0 ECF 1 0 SU01306 Reset Value = 00H CCF1 CCF0 1 0 SU01307 ...

Page 23

... CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. 23 Preliminary specification XA-S3 Reset Value = 00H PWMn ECCFn 1 0 SU01308 ...

Page 24

... CCF4 CCF3 CCF2 CCAPnL (TO CCFn) MATCH CL ECOMn CAPPn CAPNn MATn TOGn Figure 15. PCA Compare Mode 24 Preliminary specification XA-S3 CCON CCF0 (41AH) PCA INTERRUPT PCA TIMER/COUNTER CH CL CCAPnH CCAPnL CCAPMn ECCFn (491H–495H) SU01309 CCON CCF1 CCF0 (41AH) PCA INTERRUPT ...

Page 25

... CL < CCAPnL ENABLE 8–BIT COMPARATOR CL >= CCAPnL CL OVERFLOW PCA TIMER/COUNTER CAPPn CAPNn MATn TOGn PWMn Figure 17. PCA PWM Mode 25 Preliminary specification XA-S3 CCON CCF1 CCF0 (41AH) PCA INTERRUPT TOGGLE CEXn CCAPMn, n: 0..4 PWMn ECCFn (491H–495H SU01311 0 CEXn 1 CCAPMn, n: 0..4 ECCFn (491H– ...

Page 26

... Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 16 2 count of the PCA timer. 26 Preliminary specification XA-S3 CMOD CPS1 CPS0 ECF (490H) RESET CCAPM4 ...

Page 27

... This allows polling for UART errors quickly at the interrupt service routine. Baud rate sources may be timer 1 or timer 2. The XA-S3 includes 2 UART ports that are compatible with the enhanced UART used on the XA-G3. The UART has separate interrupt vectors for each UART’s transmit and receive functions ...

Page 28

... T1 overflow or fixed clock, and the UARTs could run independently with different baud rates. bit5 T2CON 0x418 RCLK0 bit5 T2MOD 0x419 RCLK1 Prescaler Select for Timer Clock (TCLK) bit3 SCR 0x440 PT1 28 Preliminary specification XA-S3 Osc/4 Osc/16 Osc/64 reserved bit4 TCLK0 bit4 TCLK1 bit2 PT0 ...

Page 29

... Slave 0 requires bit 0 and it ignores bit 1. Slave 1 requires bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires bit 1. A unique address for slave 1 would be 29 Preliminary specification XA-S3 LSB BRn OEn STINTn SU00607B ...

Page 30

... MSB SM0 SM1 SM2 REN SM1 Mode Description Baud Rate 0 0 shift register f /16 OSC 1 1 8-bit UART variable 0 2 9-bit UART f /32 OSC 1 3 9-bit UART variable Figure 21. Serial Port Control (SnCON) Register 30 Preliminary specification XA-S3 LSB TB8 RB8 TI RI SU00597C ...

Page 31

... The latched values of EA and BUSW are NOT automatically updated when an internal reset occurs. RSTOUT may be used to apply an external reset to the XA-S3 in order to update the previously latched EA and BUSW values. However, since RSTOUT reflects ALL reset sources, it cannot simply be fed back into the RST pin without other logic ...

Page 32

... IEL or IEH registers). Only three bits of the IPA register values are used on the XA-S3. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5. The value 0 in the IPA field gives the interrupt priority 0, in effect disabling the interrupt ...

Page 33

... SWE1 0104–0107 SWE2 0108–010B SWE3 010C–010F SWE4 0110–0113 SWE5 0114–0117 SWE6 0118–011B SWE7 33 Preliminary specification XA-S3 INTERRUPT ARBITRATION PRIORITY RANKING IPA0.2–0 (PX0) 2 IPA0.6–4 (PT0) 3 IPA1.2–0 (PX1) 4 IPA1.6–4 (PT1) 5 IPA2.2–0 (PT2) 6 IPA2.6–4 (PPC) 7 IPA3.2– ...

Page 34

... –1 must be externally limited as follows Preliminary specification XA-S3 RATING UNIT –55 to +125 C –65 to +150 +13.0 V –0 +0 1.5 W LIMITS UNIT UNIT MIN TYP MAX ...

Page 35

... This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design. 2000 Dec 01 TEST CONDITIONS TEST CONDITIONS Port Commercial temperature range Industrial temperature range REF– – 100 kHz 35 Preliminary specification XA-S3 LIMITS UNIT UNIT MIN MAX 2.7 3.3 V 2.5 mA 2.5 A ...

Page 36

... MHz. C 2000 Dec 01 TEST CONDITIONS TEST CONDITIONS Port Commercial temperature range Industrial temperature range REF– – 100 kHz 36 Preliminary specification XA-S3 LIMITS UNIT UNIT MIN MAX 2.7 3.3 V 2.5 mA 2.5 A 100 A 150 A AV – ...

Page 37

... Center of a step of the actual transfer curve. 2000 Dec 01 (2) (1) (5) (4) (3) 1 LSB (ideal 250 251 1 LSB = Figure 25. ADC Conversion Characteristic 37 Preliminary specification XA-S3 Offset Gain error error Full Scale error FS e 252 253 254 255 256 AV (LSB ...

Page 38

... WTL NOTES ON PAGE 41. 2000 Dec 01 = – +85 C for industrial. amb PARAMETER PARAMETER ( ( ( ( ( (V12 * t (V13 * t (V11 * t ( (V11 * t (V10 * t 38 Preliminary specification XA-S3 LIMITS UNIT UNIT MIN MAX 0 30 MHz – ...

Page 39

... Philips Semiconductors XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range AC ELECTRICAL CHARACTERISTICS (5 V RANGE) (continued) This set of parameters is referenced to the XA-S3 clock output. SYMBOL SYMBOL FIGURE FIGURE Address Cycle t 26 CLKOUT rising edge to ALE rising edge ...

Page 40

... Dec 01 = – +85 C for industrial. amb PARAMETER PARAMETER ( ( ( ( ( (V12 * t (V13 * t (V11 * t ( (V11 * t (V10 * t 40 Preliminary specification XA-S3 LIMITS UNIT UNIT MIN MAX ) – – /2) – – /2) – ( – ...

Page 41

... Philips Semiconductors XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range AC ELECTRICAL CHARACTERISTICS (3 V RANGE) (continued) This set of parameters is referenced to the XA-S3 clock output. SYMBOL SYMBOL FIGURE FIGURE Address Cycle t 26 CLKOUT rising edge to ALE rising edge ...

Page 42

... Please note that the XA-S3 requires that extended data bus hold time (WM0 = used with external bus write cycles. 7. Applies only to an external clock source, not when a crystal is connected to the XTAL1 and XTAL2 pins. ...

Page 43

... Figure 27. External Program Memory Read Cycle (Non-ALE Cycle) 2000 Dec CLLL CHPL t CHAX t PLPH t LLPL t t AVLL LLAX t PLIV A4–A11 or A4–A23 t AVIVA A0 or A1–A3, A12–A23 t AVIVB A0 or A1–A3, A12–A23 43 Preliminary specification XA-S3 t CHPH t PHIZ t CHIZ t t IVCH CHIX t PHIX INSTR IN* t IXUA SU00943A INSTR IN* SU00949 ...

Page 44

... Figure 29. External Data Memory Read Cycle (Non-ALE Cycle) 2000 Dec 01 t CHRL t RLRH t LLRL t t AVLL LLAX t RLDV A4–A11 or A4–A23 t AVDVA A0 or A1–A3, A12–A23 t AVDVB A0–A3, A12–A23 44 Preliminary specification XA-S3 t CHRH t RHDZ t CHDZ t t DVCH CHDX t RHDX DATA IN* t DXUA SU00944 D0–D7 SU00950A ...

Page 45

... A4–A11 or A4–A23 DATA OUT* t AVWL A0 or A1–A3, A12–A23 Figure 30. External Data Memory Write Cycle t t CHWTH CHWTL t (The dashed line shows the strobe without WAIT.) WTL Figure 31. WAIT Signal Timing 45 Preliminary specification XA-S3 t CHWH t CHQZ t CHQX t WHQX t UAWH SU00945 SU01068 ...

Page 46

... DD Figure 33. AC Testing Input/Output +0.1V TIMING REFERENCE POINTS –0.1V /V level occurs Figure 34. Float Waveform (NC) CLOCK SIGNAL SU00591B Figure 36 Preliminary specification XA-S3 SU00842 SU00703A V –0. +0. 20mA SU00011 RST EA XTAL2 ...

Page 47

... Tests in Active and Idle Modes CLCH CHCL RST EA (NC) XTAL2 XTAL1 V SS SU00585A Test Condition, Power Down Mode DD All other pins are disconnected 5 Preliminary specification XA-S3 Max. I (Active) DD Typical I (Active) DD Max. I (Idle) DD Typical I (Idle SU01228 SU00608A ...

Page 48

... Same as 3, external execution is disabled. Internal data RAM is not accessible. NOTES – programmed. U – unprogrammed. 2. Any other combination of the security bits is not defined. ROM CODE SUBMISSION When submitting ROM code for the XA-S3, the following must be specified: 1. 32k byte user ROM data 2. ROM security bits. ADDRESS CONTENT ...

Page 49

... Philips Semiconductors XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range PLCC68: plastic leaded chip carrier; 68 leads; pedestal 2000 Dec 01 49 Preliminary specification XA-S3 SOT188-3 ...

Page 50

... Philips Semiconductors XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range LQFP80: plastic low profile quad flat package; 80 leads; body 1.4 mm 2000 Dec 01 50 Preliminary specification XA-S3 SOT315-1 ...

Page 51

... Philips Semiconductors XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V UARTs address range 2000 Dec 01 NOTES 51 Preliminary specification XA-S3 ...

Page 52

... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2000 Dec 01 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 52 Preliminary specification XA-S3 All rights reserved. Printed in U.S.A. Date of release: 12-00 9397 750 07816 ...

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