XA-H3 NXP Semiconductors, XA-H3 Datasheet
XA-H3
Related parts for XA-H3
XA-H3 Summary of contents
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... XA-H3 CMOS 16-bit highly integrated microcontroller Preliminary specification IC28 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 1999 Sep 24 ...
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... SCP/SPI Bus NOTE: 1. Can be used as additional counters if not needed as BRGs. 1999 Sep 24 The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The XA-H3/H4 devices are members of the Philips XA (eXtended Architecture) family of high performance 16-bit microcontrollers. The XA-H3 and XA-H4 are designed to significantly minimize the need for external components. ...
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... VDD 20 A16 21 MOLD MARK A17 22 A18 23 A19 1999 Sep 24 Freq (MHz) 30 MOLD MARK XA-H3 Top View 100 Pin LQFP Part Number: PXAH30KFBE LQFP Package = SOT407-1 3 Preliminary specification XA-H3 Package Drawing Number SOT407-1 75 P1.7_BRG2 74 P1.6_RTS2 73 P1.5_CTS2 72 P1.4_CD2 71 P1.3_TRClk2 70 P1.2_RTClk2 69 P1.1_TxD2 68 P1.0_RxD2 67 P3.7_Int1_TRClk1 66 P3.6_TxD1 65 P3 ...
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... Philips Semiconductors CMOS 16-bit highly integrated microcontroller LOGIC SYMBOL XA-H3 MISC. UART1 Int2 CS4 RTClk1 CS5 ResetOut, Timer0 Timer1 Int1 TRClk1 UART3 RTClk3 ComClk, TRClk3 UART2 RTClk2 TRClk2 UART0 TRClk0 RTClk0 GPOut 1999 Sep Int0 PORT3 CD1 3.0 3.1 RTS1 3.2 3.3 BRG1 3.4 CTS1 3 ...
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... Philips Semiconductors CMOS 16-bit highly integrated microcontroller XA-H3 BLOCK DIAGRAM 256 Bytes Data SRAM Port 0 Port 1 Port 2 Port 3 Timer 0 Timer 1 Watchdog Timer 1999 Sep 24 XA-H3 CPU Core Data MMR Bus SFR Bus Memory Bus Controller 6 Chip Selects Dynamic Bus Sizing Dynamic Bus Timing ...
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... Philips Semiconductors CMOS 16-bit highly integrated microcontroller XA-H3 MEMORY MAPS *In either memory architecture, the XA-H3 can support a maximum because each of six Chip Selects is capable each. In Unified architecture, Code and Data can share the same physical Memory Chip and address space. Code Space + Data Space = 6 MB Maximum Total with 1 MB per Chip Select. Each CS (and thus space) can support either Code or Data in Harvard architecture ...
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... Chip Select 1*: Chip Selects 1 through 5 come out of reset disabled. They function as normal chip selects on the H3. CS1 can be “swapped” with CS0 (see the SWAP operation in the “Memory Controller” chapter of the XA-H3 User Manual .) CS1 is usually mapped to be based at 000000h after the swap, but is capable of being based anywhere in the 16 MB address space. ...
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... I/O P1.5_CTS2: Port 1 Bit 5, or UART2 Clear To Send input P1.6 74 I/O P1.6_RTS2: Port 1 Bit 6, or UART2 Request To Send output P1.7 75 I/O P1.7_BRG2: Port 1 Bit 7, or BRG output, or TxClk output (see UART clk diagrams in the XA-H3 User Manual .) P2.0 80 I/O P2.0_RxD3: Port 2 Bit 0, or UART3 Rx Data input P2.1 81 I/O P2.1_TxD3: Port 2 Bit 1, or UART3 Tx Data output P2 ...
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... Base Low and High) registers. Bit Functions and Addresses MSB WARNING – Never write to the BCR register in the XA-H3 – initialized to 07h, the only legal value. This is not the same as for some other XA derivatives. WARNING – Immediately after reset, always write BTRH = 51h, followed by writing BTRL = 40h in that order ...
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... SWR7 SWR6 SWR5 SWR4 287 286 285 284 283 TF1 TR1 TF0 TR0 IE1 GATE C GATE 10 Preliminary specification XA-H3 Reset Value LSB 222 221 220 – PD IDL 00h 20A 209 208 IM2 IM1 IM0 ...
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... SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4. 1. The XA-H3 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide . All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in the upper byte ...
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... Master Interrupt control R/W 8 854h Miscellaneous Tx/Rx control register R/W 8 856h Clock Mode Control R/W 8 858h Lower Byte of Baud rate time constant R/W 8 85Ah Upper Byte of Baud rate time constant 12 Preliminary specification XA-H3 Reset Description Value 00h xx xx 00h 00h 00h 00h 00h xx 00h 00h xx f8h ...
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... Interrupt Pending Bits 8 8ACh Reserved – do not write 8 8AEh Reserved – do not write RO 8 8B0h Receive Buffer 8B2h RO 8 8B4h Clock status 8B6-8BEh 13 Preliminary specification XA-H3 Reset Description Value xx f8h 00h 00h 00h xx xx 00h 00h 00h 00h 00h xx 00h ...
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... Byte 0 = older, 10Dh = Byte 1 = younger R/W 16 10Eh 10Eh = Byte 2 = older, 10Fh = Byte 3 = younger R/W 8 110h Control Register R/W 8 111h Control & Status Register R/W 8 112h Points data segment 14 Preliminary specification XA-H3 Reset Description Value 00h xx xx 00h 00h 00h 00h 00h xx 00h 00h xx f8h 00h 00h – ...
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... Current Address pointer A15 – A0 R/W 16 14Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. R/W 16 14Ch 14C = Byte0 = older 14D = Byte 1 = younger 15 Preliminary specification XA-H3 Reset Description Value 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h ...
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... Same as above, for Rx3 R/W 16 210h DMA Interrupt Flags R/W 8 260h GPOut[7] drives pin 98 (GPOut) through an inverter. GPOut[6-0] are unused, and must be written with zeroes. 16 Preliminary specification XA-H3 Reset Description Value 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 00h 00h ...
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... XInt2 FUNCTIONAL DESCRIPTION The XA-H3 functions are described in the following sections. Because all blocks are thoroughly documented in either the IC25 XA Data Handbook , or the XA-H3 User Manual , only brief descriptions are given in this datasheet, in conjunction with references to the appropriate document. XA CPU The CPU MHz implementation of the standard XA CPU core. ...
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... Because ResetOut does not reflect ResetIn, the ResetOut pin can be tied directly back into the ResetIn pin without other PC board logic. This configuration will make all resets (internal or external) appear to the XA as external resets. See the XA-H3 User Manual for a full discussion of the reset functions. ResetIn The ResetIn function is the standard XA-G3 ResetIn function ...
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... WARNING: On the external bus, ALL XA-H3 reads are 16-bit Reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus 8-bit bus, this will appear as two consecutive 8-bit reads even though the CPU instruction specified a byte read ...
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... The 16-bit wide RAM does not need the A0 pin from the processor. During byte writes to the RAM, the A0 value will cause either BLE or BHE pin to go active from the XA-H3, but not to both. For all Word Writes, Word Reads, Code Fetches, and Byte Reads, both BLE and BHE will go active ...
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... The four Tx channels have three DMA modes specifically designed for various applications of the attached UARTs. These modes are summarized in the following table. Full details for all DMA functions can be found in the DMA chapter of the XA-H3 User Manual . Maskable Interrupt On stop DMA channel picks up header from memory at end of transmission ...
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... DMA Control Register: Contains the master mode select and interrupt enable bits for the channel. 22 Preliminary specification XA-H3 Description The DMA channel runs until commanded to stop by the processor. It generates a maskable interrupt once per n bytes, where n is the number written once into the byte count register by the processor, thus an interrupt is generated once every n received bytes ...
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... The XA-H3 has a standard XA CPU Interrupt Controller, implemented with 15 Maskable Event Interrupts. Event Interrupts are defined as maskable interrupts usually generated by hardware events. However, in the XA-H3 the 15 Event Interrupts are generated by software writing directly to the interrupt flag bit. These 4 interrupts are referred to as High Priority Software Interrupts. ...
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... CD2 UART2/ RxD3 UART3 CTS3 CD3 INT0 INT1 Timer 0 Timer 1 High Priority Software Ints HSWR 3–0 1999 Sep 24 DMAH DMAL Interrupt Enable/ Disable Bits 4 Figure 6. XA-H3 Interrupt Structure Overview 24 Preliminary specification XA-H3 XA Core Interrupt Controller Master Interrupt Enable To XA CPU “EA” SU01241 ...
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... Vector Address 0000–0003 0004–0007 0008–000B 000C–000F 0010–0013 0014–0017 0040–007F 25 Preliminary specification XA-H3 Group Flag Bit Master Enable Bit MMR Hex Offset MMR Hex Offset Even Channel Rx IP UART0/1 Master Interrupt Enable RR3[5] WR9[3] 826[5] ...
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... ET0 426[1] 331 0083–0080 EX0 426[0] 330 Vector Address 0100–0103 0104–0107 0108–010B 010C–010F 0110–0113 0114–0117 0118–011B 26 Preliminary specification XA-H3 Priority Register Bit Arb. Rank Field (SFR) PHSWR3 17 4A7[6:4] PHSWR2 16 4A7[2:0] PHSWR1 15 4A6[6:4] PHSWR0 14 4A6[2:0] ...
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... (NOTE: This is +85 C specification for Preliminary specification XA-H3 Rating Unit –55 to +125 C –65 to +150 C –0 +0 1.5 W Limits Unit Unit Min Typ Max ...
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... ClkOut pF. 5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details. 6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from bytes long 16-bit bus, A3 – ...
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... ClkOut pF. 5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details. 6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from bytes long 16-bit bus, A3 – ...
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... DIS Figure 7. Read on 16-Bit Bus t CHAV t CHAV Address + DIH DIH Note 2 Note DIS DIS Figure 8. Burst Code Fetch on 16-Bit Bus 30 Preliminary specification XA-H3 t CHAH (Does Not Include A0) (Note 2) SU01277 Address + 4 t CHSH t OHDE t DIH (Note 2) t DIS Driven by XA SU01131 ...
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... Sep 24 t CHSH t CHSL t SHAH Note 1 t SHDH t CHAV t CHSL t CHSH Note 3 t Note 2 t DIS DIS Figure 10. Read (16-Bit or 8-Bit Bit Bus 31 Preliminary specification XA-H3 SU01278 t AHDR t OHDE t DIH Note 2 Driven by XA SU01283 ...
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... DIH DIS DIH DIS Note 2 Note 2 LS Byte MS Byte LS Byte Figure 11. Burst Code Fetch on 8-bit bus t SHAH t SHDH Figure 12. 16-Bit Write on 8-Bit Bus 32 Preliminary specification XA-H3 t CHAV Address + 3 t CHSH DIH DIS DIH Note 2 Note 2 MS Byte SU01245 t CHSH t SHAH ...
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... Setup time of WAIT to rising edge of ClkOut – Hold time of WAIT after ClkOut High. WH 1999 Sep 24 0 – 0 CHCL CLCX t C Figure 13. External Clock Input Drive t CODH Figure 14. ClkOut Duty Cycle Figure 15. External WAIT Pin Timing 33 Preliminary specification XA-H3 t CHCX t CLCH SU01146 SU01147 SU01148 ...
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... Philips Semiconductors CMOS 16-bit highly integrated microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 1.4 mm 1999 Sep 24 34 Preliminary specification XA-H3 SOT407-1 ...
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... Philips Semiconductors CMOS 16-bit highly integrated microcontroller 1999 Sep 24 NOTES 35 Preliminary specification XA-H3 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 1999 Sep 24 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 36 Preliminary specification XA-H3 All rights reserved. Printed in U.S.A. Date of release: 09-99 9397 750 06431 ...