XA-H3 NXP Semiconductors, XA-H3 Datasheet - Page 21

• Manufacturer Part Number: XA-H3
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4. Memory interface control registers
EIGHT CHANNEL DMA CONTROLLER
The XA-H3/H4 has eight DMA channels; one Rx DMA channel
dedicated to each UART Receive (Rx) channel, and one Tx DMA
channel dedicated to each UART Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
Table 5. Tx DMA modes summary
Receive DMA Channel Modes
The Rx DMA channels have two DMA modes specifically designed
for various applications of the attached UARTs. These modes are
1999 Sep 24
MRBH
MRBL
MICFG
MBCL
BiCFG
BiAM
BiTMG
Tx
Chaining
Stop on TC
Periodic
Interrupt
CMOS 16-bit highly integrated microcontroller
Mode
“MMR Base Address” High
“MMR Base Address” Low
MIF Configuration
Memory Bank Configuration Lock
Bank i Configuration
Bank i Base Address
Bank i Timing
Header in memory
Processor loads Byte Count Register
Loaded by processor into DMA, used by
DMA only to determine the number of
bytes between interrupts. Processor can
calculate the byte count from the DMA
address pointer.
Register Name
Byte Count Source
SFR
8 bits
SFR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
Type
Reg
This SFR is used to relocate the MMRs. It contains address bits a23 – a16 of the
base address for the 4 kB Memory Mapped Register space. See the User Manual for
using this SFR to relocate the MMRs.
Contains address bits a15 – a12 of the base address for the 4 kB Memory Mapped
Register space.
Contains the CLKOUT Enable bit.
Contains the bits for locking and unlocking the BiCFG Registers.
Contains the size, type, bus width, and enable bits for Memory Bank i.
Contains the base address bits for Memory Bank i.
Contains the timing control bits for Memory Bank i.
On stop
Byte count completed
(Tx DMA stops)
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte
count register.
Maskable Interrupt
21
Transmit DMA Channel Modes
The four Tx channels have three DMA modes specifically designed
for various applications of the attached UARTs. These modes are
summarized in the following table. Full details for all DMA functions
can be found in the DMA chapter of the XA-H3 User Manual .
summarized in the following table. For full details on implementation
and use, see the XA-H3 User Manual .
DMA channel picks up header from memory at end of
transmission. If byte count in header is greater than zero,
then DMA transmits the number of bytes specified in the
byte count. If byte count equals 0, then a maskable
interrupt is generated. This process repeats until byte count
in data header is zero. See XA-H3 User Manual for details.
Processor loads byte count into DMA. DMA sends that
number of bytes, generates maskable interrupt, and stops.
DMA runs until commanded to stop by processor. CPU
loaded value in Byte Count Register is used to generate
an interrupt for every n bytes. Every time byte counter
rolls over, a new maskable interrupt is generated.
Description
Description
Preliminary specification
XA-H3