XA-H3 NXP Semiconductors, XA-H3 Datasheet - Page 31

The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking

XA-H3

Manufacturer Part Number
XA-H3
Description
The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
1999 Sep 24
CMOS 16-bit highly integrated microcontroller
On all cycles on 8-bit bus, BHE remains high (inactive)
Note:
WARNING: Some 8-bit I/O devices (especially FIFOS) cannot operate correctly with 2 bytes being read for a one byte read. The most common (and least expensive)
solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this tech-
nique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
BHE/BLE
On the external bus, ALL XA-H4 reads are 16-bit reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the
extra byte. Thus, “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear as two consecutive 8-bit reads even
though the CPU will only use one of the two bytes.
ClkOut
A19 – A1
D7 – D0
WE
CS
ClkOut
D
A
BLE
CS
OE
A0
Driven by XA
t
CHAV
t
CHDV
Figure 9. Write ( byte write on 8-bit bus, or all writes on 16-bit bus )
t
AVSL
t
AVSL
Figure 10. Read (16-Bit or 8-Bit) on 8 Bit Bus
t
Note 1
CHSL
t
CHSL
Note 3
t
DIS
t
CHSH
31
Note 2
t
CHAV
t
t
SHAH
SHDH
t
CHSH
t
DIS
Note 2
t
DIH
t
OHDE
Driven by XA
t
AHDR
SU01278
Preliminary specification
XA-H3
SU01283

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