XA-H3 NXP Semiconductors, XA-H3 Datasheet - Page 2

• Manufacturer Part Number: XA-H3
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

1. Can be used as additional counters if not needed as BRGs.
Philips Semiconductors
DESCRIPTION
The powerful 16-bit XA CPU core and rich feature set make the
XA-H3 and XA-H4 devices ideal for high-performance real-time
applications such as industrial control and networking. By supporting
of up to 32 MB of external memory, these devices provide a low-cost
solution to embedded applications of any complexity. Features like
DMA, memory controller and four advanced UARTs help solve I/O
intensive tasks with a minimum of CPU load.
FEATURES
Table 1. XA-H3 and XA-H4 features comparison
NOTE:
Maximum External Memory
(Harvard Memory Mode)
Maximum External Memory (Unified Memory Mode)
Memory Controller supports both Harvard and Unified architectures
De-multiplexed Address/Data Bus
DRAM Controller
DMA Channels
Dynamic Bus Sizing
Dynamic Bus Timing
Programmable Chip Selects
General Purpose IO Pins
Potential Interrupt Pins
Interrupts (programmable priority)
Counter/Timers
Baud Rate Generators
Serial Ports
Maximum Serial Data Rates
Match Characters
Hardware Autobaud
SCP/SPI Bus
1999 Sep 24
Large Memory Support (up to 6 MB external)
De-multiplexed Address/Data Bus
Six Programmable Chip Selects
– Support for Unified Memory – allows easy user modification of
– External ISP Flash support for easy code download
Dynamic Bus Sizing – each of 6 Chip Selects can be programmed
for 8-bit or 16-bit bus.
CMOS 16-bit highly integrated microcontroller
all code
1
Feature
2
asynch to 230.4 kbps (no sync)
The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The
XA-H3/H4 devices are members of the Philips XA (eXtended
Architecture) family of high performance 16-bit microcontrollers.
The XA-H3 and XA-H4 are designed to significantly minimize the
need for external components.
Dynamic Bus Timing – each of 6 chip selects has individual
programmable bus timing.
32 Programmable General Purpose I/O Pins
Four UARTs with 230.4 kbps capability
Eight DMA Channels
13 Hardware Event
4 High Priority SW
2 plus Watchdog
7 Standard SW
4 UARTS
XA-H3
6 MB
6 MB
Yes
Yes
Yes
Yes
No
No
No
No
33
16
8
6
4
(16 MB Code, 16 MB Data)
4 async chars per USART
asynch to 230.4 kbps
13 Hardware Event
4 High Priority SW
Preliminary specification
2 plus Watchdog
up to 230.4 kbps
7 Standard SW
sync to 1 Mbps
4 USARTS
XA-H4
32 MB
16 MB
Yes
Yes
Yes
Yes
Yes
33
16
8
6
4
XA-H3