XA-H3 NXP Semiconductors, XA-H3 Datasheet - Page 18

• Manufacturer Part Number: XA-H3
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Timers 0 and 1
Timers 0 and 1 are the standard XA-G3 timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the
IC25 XA Data Handbook for details. Many XA derivatives include a
standard XA Timer 2. The Timer 2 block has been removed in order
to provide other functions on the XA-H3.
Watchdog Timer
This timer is a standard XA-G3 Watchdog Timer. See the G3
datasheet in IC25. Also, if you intend to use the Watchdog Timer to
assert the ResetOut pin, see “ResetOut” in the XA-H3 User Manual .
The Watchdog Timer is enabled at reset, and must be periodically
fed to prevent timeout. If the watchdog times out, it will generate an
internal reset; and if ResetOut is enabled the internal reset will
generate a ResetOut pulse (active low pulse on ResetOut pin.)
Reset
On the XA-H3 there are two pins associated with reset. The ResetIn
pin provides an external reset into the XA-H3. The port pin
P3.2_Timer0_ResetOut output can be configured as ResetOut.
Because ResetOut does not reflect ResetIn, the ResetOut pin can
be tied directly back into the ResetIn pin without other PC board
logic. This configuration will make all resets (internal or external)
appear to the XA as external resets. See the XA-H3 User Manual for
a full discussion of the reset functions.
ResetIn
The ResetIn function is the standard XA-G3 ResetIn function. The
ResetIn signal does NOT get passed on to ResetOut. See the
XA-H3 User Manual for details on reset.
MEMORY CONTROLLER AND I/O BUS INTERFACE
The Memory Controller and bus interface generate bus cycles that are
designed to service SRAMs, Flash, EEPROM, peripheral chips, etc.
The XA-H3 has a highly programmable memory bus interface. Most
SRAMs, Flash, ROMs, and peripheral chips can be connected to this
1999 Sep 24
CMOS 16-bit highly integrated microcontroller
RSTSRC
Not Bit Addressable
Reset Value = see below
WARNING:
If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes
precedence over internal reset.
BIT
RSTSRC.7 ROEN
RSTSRC.6 –
RSTSRC.5 –
RSTSRC.4 –
RSTSRC.3 –
RSTSRC.2 R_WD
RSTSRC.1 R_CMD
RSTSRC.0 R_EXT
SYMBOL
Reg Type and Address = SFR 463h
MSB
ROEN
FUNCTION
ResetOut function enable bit – see XA-H3 User Manual for details
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.)
Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.)
Indicates that the last reset was caused by the external ResetIn input.
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Figure 2. RSTSRC Reset Source Register
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ResetOut
The P3.2_Timer0_ResetOut pin provides an external indication (if the
ResetOut function is enabled in the RSRSRC register) via an active
low output when an internal reset occurs (internal reset is Reset
instruction or Watchdog time out.) If the ResetOut function is enabled,
the ResetOut pin will be driven low when a Watchdog reset occurs or
the Reset instruction is executed. This signal may be used to inform
other devices in the system that the XA-H3 has been internally reset.
The ResetIn signal does NOT get passed on to ResetOut. When
activated, the duration of the ResetOut pulse is 256 system clocks.
WARNING: At power on time, from the time that power coming up is
valid, the P3.2_Timer0_ResetOut pin may be driven low for any
period from zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Reset Source Register
The reset source identification register (RSTSRC) indicates the cause
of the most recent XA reset. The cause may have been an externally
applied reset signal, execution of the RESET instruction, or a
Watchdog reset. Figure 2 shows the fields in the RSTSRC register. If
the ResetOut function is tied back into the ResetIn pin, then all resets
will be external resets, and will thus appear as external resets in the
reset source register. RSTSRC[7] enables the ResetOut function; 1 =
Enabled, 0 = Disabled. See XA-H3 User Manual for details;
RSTSRC[7] differs in function from most other XA derivatives.
interface with no external decode logic or interface chips. The bus
interface provides 6 mappable chip select outputs. The bus timing for
each individual memory bank or peripheral can be programmed to
accommodate slow or fast devices, with various bus protocols.
R_WD
R_CMD
R_EXT
LSB
Preliminary specification
XA-H3
SU01237