XA-S3 NXP Semiconductors, XA-S3 Datasheet - Page 14



Manufacturer Part Number
The XA-S3 device is a member of Philips Semiconductors? XA(eXtended Architecture) family of high performance 16-bitsingle-chip microcontrollers
NXP Semiconductors
complete a conversion, and the timing must be set differently in ADCFG.
Philips Semiconductors
Details of XA-S3 functions will be described in the following sections.
Analog to Digital converter
The XA-S3 has an 8-channel, 8-bit A/D converter with 8 sets of result
registers, single scan and multiple scan operating modes. The A/D
also has a 10-bit conversion mode that provides greater result
resolution. The A/D input range is limited to 0 to AV
The A/D inputs are on Port 5. Analog Power and Ground as well as
be used. Prior to enabling the A/D converter or driving analog signals
into the A/D inputs, the port configurations for the pins being used as
A/D inputs must be set to the “off” (high impedance, input only) mode.
A/D timing can be adapted to the application clock frequency in
order to provide the fastest possible conversion.
A/D converter operation is controlled through the ADCON (A/D Control)
register, see Figure 1. Bits in ADCON start and stop the A/D, flag
conversion completion, and select the converter operating modes. When
10-bit resolution is needed, the A/D mode may be set to give 10 result
bits by setting the ADRES bit to 1. In this mode, the A/D takes longer to
A/D Conversion Modes
The A/D converter supports a single scan mode and a continuous
scan mode. In either mode, one or more A/D channels may be
converted. The ADCS register determines which channels are
converted. If the corresponding bit in the ADCS register is set, that
channel is selected for conversions, otherwise that channel is
skipped. The ADCS register is detailed in Figure 2.
For any A/D conversion, the results are stored in ADRSHn,
corresponding to the A/D channel just converted. For a 10-bit
conversion, the two least significant bits are read from the upper end
2000 Dec 01
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
Bit Addressable
Reset Value: 00h
C, 2 UARTs, 16 MB address range
and AV
must be supplied in order for the A/D converter to
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Selects 8-bit (0) or 10-bit (1) conversion mode.
A/D mode select.
A/D start and status. Setting this bit by software starts the A/D conversion of the selected A/D
inputs. ADSST remains set as long as the A/D is in operation. In continuous conversion mode,
ADSST will remain set unless the A/D is stopped by software. While ADSST is set, new start
commands are ignored. An A/D conversion is progress may be aborted by software clearing
A/D conversion complete/interrupt flag. This flag is set when all selected A/D channels are
converted in either the single scan or continuous scan modes. Must be cleared by software.
1 = continuous scan of selected inputs after a start of the A/D.
0 = single scan of selected inputs after a start of the A/D.
Figure 1. A/D Control Register (ADCON)
(3.3 V max.).
A/D conversions are begun by setting the A/D Start and STatus bit in
application. Because A/D operation is mostly dependent on real-time
of register ADRSL. These bits must be read before another
conversion is begun.
ADCON. In the single scan mode, all of the channels selected by
bits in the ADCS register will be converted once. The ADINT flag is
set when the last channel is converted. In the continuous scan
mode, the A/D converter continuously converts all A/D channels
selected by bits in the ADCS register. The ADINT flag is set when all
channels have been converted once.
The A/D converter can generate an interrupt when the ADINT flag is
set. This will occur if the A/D interrupt is enabled (via the EAD bit in
IEL), the interrupt system is enabled (via the EA bit in IEL), and the
A/D interrupt priority (specified in IPA3 bits 3 to 0) is higher than the
currently running code (PSW bits IM3 through IM0) and any other
pending interrupt. ADINT must be cleared by software.
A/D Timing Configuration
The A/D sampling and conversion timing may be optimized for the
particular oscillator frequency and input drive characteristics of the
effects (charging time of sampling capacitors, settling time of the
comparator, etc.), A/D conversion times are not necessarily much
longer at slower clock frequencies. The A/D timing is controlled by
the ADCFG register, as shown in Figure 3, Table 2 and Table 3.
The primary effect of ADCFG settings is to adjust the A/D sample
and hold time to be relatively constant over various clock
frequencies. Two settings (value 6 and B) are provided to allow fast
conversions with a lower external source driving the A/D inputs.
These settings provide double the sample time at the same
frequency. Of course, settings intended for lower frequencies may
also be used at higher frequencies in order to increase the A/D
sampling time, but this method has the side effect of significantly
increasing A/D conversion times.
Preliminary specification

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