LH75401_LH75411_N NXP Semiconductors, LH75401_LH75411_N Datasheet

The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices

LH75401_LH75411_N

Manufacturer Part Number
LH75401_LH75411_N
Description
The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
Manufacturer
NXP Semiconductors
Datasheet
COMMON FEATURES
Preliminary data sheet
DESCRIPTION
sists of two low-cost 16/32-bit System-on-Chip (SoC)
devices.
• LH75401 — contains the superset of features.
• LH75411 — similar to LH75401, without CAN 2.0B.
• Highly Integrated System-on-Chip
• ARM7TDMI-S™ Core
• High Performance (84 MHz CPU Speed)
• 32 kB On-chip SRAM
• Clock and Power Management
• Eight Channel, 10-bit Analog-to-Digital Converter
• Integrated Touch Screen Controller
• Serial interfaces
• Synchronous Serial Port
• Real-Time Clock (RTC)
• Three Counter/Timers
• Low-Voltage Detector
Preliminary data sheet
The NXP BlueStreak LH75401/LH75411 family con-
– Internal PLL Driven or External Clock Driven
– Crystal Oscillator/Internal PLL Can Operate with
– 16 kB Tightly Coupled Memory (TCM) SRAM
– 16 kB Internal SRAM
– Low Power Modes: Standby, Sleep, Stop
– Two 16C550-type UARTs supporting baud rates
– One 82510-type UART supporting baud rates up
– Motorola SPI™
– National Semiconductor Microwire™
– Texas Instruments SSI
– Capture/Compare/PWM Compatibility
– Watchdog Timer (WDT)
Input Frequency Range of 14 MHz to 20 MHz
up to 921,600 baud (requires crystal frequency of
14.756 MHz).
to 3,225,600 baud (requires a system clock of
70 MHz).
• JTAG Debug Interface and Boundary Scan
• Single 3.3 V Supply
• 5 V Tolerant Digital I/O
• 144-pin LQFP Package
• −40°C to +85°C Operating Temperature
Unique Features of the LH75401
• Color and Grayscale Liquid Crystal Display (LCD)
• CAN Controller that supports CAN version 2.0B.
Unique Features of the LH75411
• Color and Grayscale LCD Controller (LCDC)
Controller
– XTALIN and XTAL32IN inputs are 1.8 V ± 10 %
– 12-bit (4,096) Direct Mode Color, up to VGA
– 8-bit (256) Direct or Palettized Color, up to SVGA
– 4-bit (16) Direct Mode Color/Grayscale, up to XGA
– 12-bit Video Bus
– Supports STN, TFT, HR-TFT, and AD-TFT
– 12-bit (4,096) Direct Mode Color, up to VGA
– 8-bit (256) Direct or Palettized Color, up to SVGA
– 4-bit (16) Direct Mode Color/Grayscale, up to XGA
– 12-bit Video Bus
– Supports STN, TFT, HR-TFT, and AD-TFT
Displays.
Displays.
LH75401/LH75411
System-on-Chip
1

LH75401_LH75411_N Summary of contents

Page 1

Preliminary data sheet DESCRIPTION The NXP BlueStreak LH75401/LH75411 family con- sists of two low-cost 16/32-bit System-on-Chip (SoC) devices. • LH75401 — contains the superset of features. • LH75411 — similar to LH75401, without CAN 2.0B. COMMON FEATURES • Highly Integrated ...

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... ORDERING INFORMATION Type number Name LH75401N0Q100C0 LQFP144 LH75411N0Q100C0 LQFP144 2 NXP Semiconductors Table 1. Ordering information Package Description plastic low profile quad flat package; 144 leads; body 1.4 mm plastic low profile quad flat package; 144 leads; body 1.4 mm Rev. 01 — 16 July 2007 ...

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... System-on-Chip LH75401 BLOCK DIAGRAM ARM7TDMI-S STATIC MEMORY CONTROLLER BROWNOUT DETECTOR LINEAR REGULATOR Preliminary data sheet NXP Semiconductors MHz 32.768 kHz OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL INTERNAL 16KB SRAM AHB INTERFACE VECTORED INTERRUPT CONTROLLER TCM 16KB SRAM 4 CHANNEL ...

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... LH75401/LH75411 LH75411 BLOCK DIAGRAM ARM 7TDMI-S STATIC MEMORY CONTROLLER BROWNOUT DETECTOR LINEAR REGULATOR 4 NXP Semiconductors MHz 32.768 kHz OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL INTERNAL 16KB SRAM AHB INTERFACE VECTORED INTERRUPT CONTROLLER TCM 16KB SRAM 4 CHANNEL DMA CONTROLLER ADVANCED ...

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... System-on-Chip PIN CONFIGURATION Figure 3. LH75401/LH75411 pin configuration Preliminary data sheet NXP Semiconductors 1 108 LH75401/ LH75411 36 73 002aad207 Rev. 01 — 16 July 2007 LH75401/LH75411 5 ...

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... PB0 nCS1 31 nCS0 32 PC7 A23 33 PC6 A22 34 VDD 35 PC5 A21 36 PC4 A20 37 PC3 A19 38 PC2 A18 6 NXP Semiconductors Table 2. LH75401 Numerical Pin List FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE I I Power None Ground None I I ...

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... PD5 INT5 74 PD4 INT4 75 VDDC 76 PD3 INT3 77 PD2 INT2 78 PD1 INT1 79 PD0 INT0 80 VSSC Preliminary data sheet NXP Semiconductors FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Ground None Power None Ground None ...

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... PG7 CTCAP0B 117 PG6 CTCAP0A 118 PG5 CTCLK 119 VSS 120 PG4 LCDVEEEN 121 PG3 LCDVDDEN 122 PG2 LCDDSPLEN 8 NXP Semiconductors FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE None None None Ground None Power None None None Ground None None None None ...

Page 9

... Signal is selectable as pull-up, pull-down pull-up/pull-down via the I/O Configuration peripheral. 2. CMOS Schmitt trigger input. 3. Signals preceded with ‘n’ are active LOW. 4. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) 5. LINREGEN activation requires a 0 Ω pull-up to VDD. Preliminary data sheet NXP Semiconductors FUNCTION FUNCTION OUTPUT 3 TYPE ...

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... DREQ Input 73 DACK Output 10 NXP Semiconductors Table 3. LH75401 Signal Descriptions DESCRIPTION MEMORY INTERFACE (MI) Static Memory Controller Write Enable Static Memory Controller Output Enable Static Memory Controller External Wait Control Static Memory Controller Byte Lane Strobe Static Memory Controller Byte Lane Strobe ...

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... CANTX Output 104 CANRX Input Preliminary data sheet NXP Semiconductors DESCRIPTION COLOR LCD CONTROLLER (CLCDC) Signal Used by the Row Driver (AD-TFT, HR-TFT only) Analog Supply Enable (AC Bias SIgnal) Digital Supply Enable LCD Panel Power Enable Reverse Signal (AD-TFT, HR-TFT only) ...

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... PC4 Input/Output General Purpose I/O Signals - Port C 37 PC3 38 PC2 39 PC1 40 PC0 12 NXP Semiconductors DESCRIPTION ANALOG-TO-DIGITAL CONVERTER (ADC) ADC Inputs TIMER 0 Timer 0 Capture Inputs Timer 0 Compare Outputs Common External Clock TIMER 1 Timer 1 Capture Inputs Timer 1 Compare Outputs Common External Clock TIMER 2 ...

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... PI0 RESET, CLOCK, AND POWER CONTROLLER (RCPC) 62 nRESETIN Input 71 nRESETOUT Output 72 INT6 Input Preliminary data sheet NXP Semiconductors DESCRIPTION General Purpose I/O Signals - Port J User Reset Input System Reset Output External Interrupt Input 6 Rev. 01 — 16 July 2007 LH75401/LH75411 NOTES ...

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... Power 97 VDDA_ADC Power NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded with ‘n’ are active LOW. 14 NXP Semiconductors DESCRIPTION External Interrupt Input 5 External Interrupt Input 4 External Interrupt Input 3 External Interrupt Input 2 External Interrupt Input 1 External Interrupt Input 0 Power-on Reset Input 32 ...

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... PC6 A22 34 VDD 35 PC5 A21 36 PC4 A20 37 PC3 A19 38 PC2 A18 39 PC1 A17 40 PC0 A16 41 VSS Preliminary data sheet NXP Semiconductors Table 4. LH75411 Numerical Pin List FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE I I Power None Ground None I/O ...

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... PD4 INT4 75 VDDC 76 PD3 INT3 77 PD2 INT2 78 PD1 INT1 79 PD0 INT0 80 VSSC 81 nPOR 82 XTAL32IN 83 XTAL32OUT 16 NXP Semiconductors FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Power None Ground None Power None ...

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... PG4 LCDVEEEN 121 PG3 LCDVDDEN 122 PG2 LCDDSPLEN 123 PG1 LCDCLS 124 PG0 LCDPS 125 PH7 LCDDCLK Preliminary data sheet NXP Semiconductors FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Ground None Power None None None Ground None None None None None None ...

Page 18

... Signal is selectable as pull-up, pull-down pull-up/pull-down via the I/O Configuration peripheral. 2. CMOS Schmitt trigger input. 3. Signals preceded with ‘n’ are active LOW. 4. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) 5. LINREGEN activation requires a 0 Ω pull-up to VDD. 18 NXP Semiconductors FUNCTION FUNCTION OUTPUT 3 TYPE ...

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... DREQ Input 73 DACK Output Preliminary data sheet NXP Semiconductors Table 5. LH75411 Signal Descriptions DESCRIPTION MEMORY INTERFACE (MI) Static Memory Controller Write Enable Static Memory Controller Output Enable Static Memory Controller External Wait Control Static Memory Controller Byte Lane Strobe Static Memory Controller Byte Lane Strobe ...

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... AN8 94 AN1 (UR/X-) 95 AN6 96 AN0 (UL/X+) 20 NXP Semiconductors DESCRIPTION COLOR LCD CONTROLLER (CLCDC) Signal Used by the Row Driver (AD-TFT, HR-TFT only) Analog Supply Enable (AC Bias SIgnal) Digital Supply Enable LCD Panel Power Enable Reverse Signal (AD-TFT, HR-TFT only) Clock to the Row Drivers (AD-TFT, HR-TFT only) ...

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... PD4 76 PD3 Input/Output General Purpose I/O Signals - Port D 77 PD2 78 PD1 79 PD0 Preliminary data sheet NXP Semiconductors DESCRIPTION TIMER 0 Timer 0 Capture Inputs Timer 0 Compare Outputs Common External Clock TIMER 1 Timer 1 Capture Inputs Timer 1 Compare Outputs Common External Clock TIMER 2 Timer 2 Capture Inputs ...

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... Input 77 INT2 Input 78 INT1 Input 79 INT0 Input 22 NXP Semiconductors DESCRIPTION General Purpose I/O Signals - Port J User Reset Input System Reset Output External Interrupt Input 6 External Interrupt Input 5 External Interrupt Input 4 External Interrupt Input 3 External Interrupt Input 2 External Interrupt Input 1 External Interrupt Input 0 Rev. 01 — ...

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... VDDA_ADC Power NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded with ‘n’ are active LOW. Preliminary data sheet NXP Semiconductors DESCRIPTION Power-on Reset Input 32.768 kHz Crystal Clock Input 32.768 kHz Crystal Clock Output Crystal Clock Input Crystal Clock Output ...

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... APB peripherals. Generally, APB peripherals are serviced by the ARM core. However, if they are DMA-enabled, they are also serviced by the DMAC to increase system performance while the ARM core runs from local internal memory. 24 NXP Semiconductors LCD TOUCH SCREEN CAN TRANSCEIVER CAN ...

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... Color LCDC (LH75401 and LH75411) 2 DMAC 3 (Lowest) ARM7TDMI-S Core (Default) Preliminary data sheet NXP Semiconductors Memory Interface Architecture The LH75401/LH75411 microcontrollers provide the following data-path management resources on chip: • AHB and APB data buses • zero-wait-state TCM SRAM accessible via processor • ...

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... SMC FEATURES • Provides four banks of external memory, each with a maximum size of 16 MB. 26 NXP Semiconductors • Supports Random Access Memory (RAM), Read Only DEVICE Memory (ROM), Flash, and burst ROM • Supports external bus and external device widths of 8 and 16 bits • ...

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... Signal polarity, active HIGH or LOW – Little Endian data format – Interrupt-generation event. Preliminary data sheet NXP Semiconductors ADVANCED LCD INTERFACE The Advanced LCD Interface (ALI) allows for direct connection to ultra-thin panels that do not include a tim- ing ASIC. It converts TFT signals from the Color LCD controller to provide the proper signals, timing and levels for direct connection to a panel’ ...

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... The Compare Registers can force the compare output pin either HIGH or LOW upon a match. 28 NXP Semiconductors The timers support a PWM Mode that uses the two Timer Compare Registers associated with a timer to create a PWM. Each timer can generate a separate interrupt ...

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... Front bias-and-control network for Touch Screen interface and support functions compatible with indus- try-standard 4- and 5-wire touch-sensitive panels Preliminary data sheet NXP Semiconductors • Touch-pressure sensing circuits • Pen-down sensing circuit and interrupt generator • Voltage-reference generator that is independently controlled • ...

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... The WDT supports 16 selectable time intervals, for a time-out of 216 through 231 system clock cycles. All Control and Status Registers for the Watchdog Timer are accessed through the APB. 30 NXP Semiconductors Table 10. SSP Modes DESCRIPTION WDT FEATURES • Counter generates an interrupt at a set interval and the count reloads from the pre-set value after reach- ing zero ...

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... Preliminary data sheet NXP Semiconductors The VIC also accepts software-generated interrupts. Software-generated interrupts use the same enabling control as hardware-generated interrupts. The VIC provides 32 interrupts: • 16 vectored interrupts • more default-vectored interrupts. Any of the 32 interrupt source lines can be assigned to any of the 16 interrupt vectors ...

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... EmbeddedICE Mode, where accesses the TAP Controller in the core and the core is placed in Debug Mode. 32 NXP Semiconductors The state of the TEST1, TEST2, and nRESETIN sig- nals determines the operating mode entered at Power- on Reset (see Table 12). Table 12. Device Operating Modes OPERATING MODE ...

Page 33

... PI6/LCDVD6 PI6 PI5/LCDVD5 PI5 PI4/LCDVD4 PI4 PI3/LCDVD3 PI3 PI2/LCDVD2 PI2 PI1/LCDVD1 PI1 PI0/LCDVD0 PI0 Preliminary data sheet NXP Semiconductors Table 14. LCD Panel Signal Multiplexing 4-BIT STN (MONOCHROME) DUAL PANEL Reserved MLSTN3 Reserved MLSTN2 Reserved MLSTN1 Reserved MLSTN0 Reserved Reserved Reserved Reserved ...

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... On-chip Linear regulator and PLL disabled; VDDC supplied externally. 2. Core speeds greater than 84 MHz require external VDDC and may not yield proper UART baud rates. 3. Core speeds greater than 70 MHz require an external clock. 4. Additional performance may be achieved in accordance with Figure 5. 34 NXP Semiconductors MINIMUM MAXIMUM -0.3 V 2 ...

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... System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC. Preliminary data sheet NXP Semiconductors Temp ( Celsius) ˚ ...

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... VIL MAX. = 0.5 V for pin TCK with 50 pF load. 2. Running a Typical Application at 51.6 MHz. Table 20. Linear Regulator DC Characteristics SYMBOL PARAMETER IQUIESCENT Quiescent Current ISLEEPLR Current when Regulator is Disabled IOLR Output Current Range VOLR Output Voltage RPULL Pull-up Resistor 36 NXP Semiconductors Table 19. DC Characteristics MIN. TYP. MAX. UNIT 2.0 0.8 2.0 0.8 0.35 2.6 2.6 2.6 2.6 0.4 0.4 0.4 0.4 1 ...

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... Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC. 4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down. Preliminary data sheet NXP Semiconductors MIN. TYP. MAX. ...

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... STEP OF THE ACTUAL 7 TRANSFER CURVE LSB OFFSET ERROR DNL 38 NXP Semiconductors IDEAL TRANSFER CURVE TRANSFER CURVE INTEGRAL NON-LINEARITY 1015 1016 1017 1018 1019 Figure 6. ADC Transfer Characteristics Rev. 01 — 16 July 2007 System-on-Chip OFFSET ...

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... FCLK = 51.6 MHz; HCLK = 51.6 MHz • All voltages at typical values • Nominal case temperature. Preliminary data sheet NXP Semiconductors PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 23 shows the typical current consumption for each of the on-board peripheral blocks. The values were deter- mined with the peripheral clock running at maximum frequency, typical conditions, and no I/O loads ...

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... Oscillator stabilization time after Power Up (VDDC = VDDCMIN) tRSTOV nPOR LOW to nPOR valid (once sampled LOW) tPORH nPOR hold extend to allow PLL to lock once XTAL is stable 40 NXP Semiconductors Table 24. Memory Interface Signals MINIMUM MAXIMUM tHCLK + × tHCLK – tHCLK – Data input valid following address valid 2 × ...

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... To assure that the current access (read or write) will be extended by nWAIT, program at least two wait states for this bank of Preliminary data sheet NXP Semiconductors tOSC32 tPORH Figure 7. Power-up Stabilization memory wait states are programmed, the SMC holds this state for N system clocks or until the SMC detects that nWAIT is inactive, whichever occurs last ...

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... LH75401/LH75411 Figure 8. External Static Memory Write, One Wait State 42 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

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... System-on-Chip Figure 9. External Static Memory Write, Two Wait States Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH75401/LH75411 43 ...

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... LH75401/LH75411 Figure 10. External Static Memory Read, One Wait State 44 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

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... System-on-Chip Figure 11. External Static Memory Read, nWAIT Active Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH75401/LH75411 45 ...

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... LH75401/LH75411 Synchronous Serial Port Waveform Figure 12. Synchronous Serial Port Waveform 46 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

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... Figure 13 shows the timing for a peripheral-to-mem- ory data transfer, where Figure 13. Peripheral-to-Memory Data-Transfer Timing Preliminary data sheet NXP Semiconductors SoSize = DeSize and SoBurst = 4. • Figure 14 shows the timing for a memory-to-periph- eral data transfer, where SoSize = DeSize and SoBurst = 4. ...

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... LH75401/LH75411 Figure 14. Memory-to-Peripheral Data-Transfer Timing 48 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

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... Timing2:IHS. STN VERTICAL TIMING Figure 16 shows typical vertical timing waveforms for STN panels. Preliminary data sheet NXP Semiconductors TFT HORIZONTAL TIMING Figure 17 shows typical horizontal timing waveforms for TFT panels. TFT VERTICAL TIMING Figure 18 shows typical vertical timing waveforms for TFT panels ...

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... LH75401/LH75411 Figure 15. STN Horizontal Timing Diagram 50 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

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... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 16. STN Vertical Timing Diagram Rev. 01 — 16 July 2007 LH75401/LH75411 51 ...

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... LH75401/LH75411 52 NXP Semiconductors Figure 17. TFT Horizontal Timing Diagram Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

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... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 18. TFT Vertical Timing Diagram Rev. 01 — 16 July 2007 LH75401/LH75411 53 ...

Page 54

... SYNCHRONIZATION PULSE) LCDVD[11:0] (LCD VIDEO DATA) NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz. Figure 20. AD-TFT, HR-TFT Vertical Timing Diagram 54 NXP Semiconductors 1 AD-TFT or HR-TFT HORIZONTAL LINE Timing0:HSW 001 002 003 004 005 006 007 008 PIXEL DATA Timing0:HSW + Timing0: HBP 001 ...

Page 55

... Tolerance for R1, C1 ≤ 5%. Figure 21. Suggested External Components, 32.768 kHz Oscillator Preliminary data sheet NXP Semiconductors Figure 22 shows the suggested external compo- nents for the 14.7456 MHz crystal circuit to be used with the NXP LH75401/LH75411. The NAND gate rep- resents the logic inside the SoC ...

Page 56

... R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1 ≤ 5%. Figure 22. Suggested External Components, 14.7456 MHz Oscillator 56 NXP Semiconductors ENABLE XTALIN Y1 14.7456 MHz R1 1 MΩ ...

Page 57

... max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT486-1 136E23 Figure 23. Preliminary data sheet NXP Semiconductors ...

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... LH75401/LH75411 144LQFP NOTE: Dimensions in mm. 58 NXP Semiconductors 21.2 0.5 17.5 Figure 24. Recommended PCB Footprint Rev. 01 — 16 July 2007 System-on-Chip 1.6 144LQFP Preliminary data sheet ...

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... REVISION HISTORY Document ID Release date Data sheet status LH75401_411_N_1 20070716 Modifications: • First NXP version based on the LH75400/01/10/11 data sheet of 20070510 Preliminary data sheet NXP Semiconductors Table 27. Revision history Change notice Preliminary data sheet - Rev. 01 — 16 July 2007 LH75401/LH75411 Supersedes LH754xx Data Sheet 5-10-07 ...

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... NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. ...

Page 61

... Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. ...

Page 62

... Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors ...

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... The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage ...

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