LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet

The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2

LPC3130_3131

Manufacturer Part Number
LPC3130_3131
Description
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features
2.1 Key features
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB
2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus
interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a single
chip targeted at consumer, industrial, medical, and communication markets. To optimize
system power consumption, the LPC3130/3131 have multiple power domains and a very
flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.
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LPC3130/3131
Low-cost, low-power ARM926EJ-S MCUs with high-speed
USB 2.0 OTG, SD/MMC, and NAND flash controller
Rev. 1 — 9 February 2009
CPU platform
Internal memory
External memory interface
Communication and connectivity
System functions
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180 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM
NAND flash controller with 8-bit ECC
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I
Integrated master/slave SPI
Two master/slave I
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Four-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface
Dynamic clock gating and scaling
Multiple power domains
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB
DMA controller
Four 32-bit timers
Watchdog timer
2
S-bus interfaces
2
C-bus interfaces
Preliminary data sheet

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LPC3130_3131 Summary of contents

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LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 1 — 9 February 2009 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up ...

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... LPC3131FET180 TFBGA180 plastic thin fine pitch ball grid array package, 180 balls, body 12 Table 2. Ordering options for LPC3130/3131 Type number Core/bus frequency LPC3130FET180 180 MHz/ 90 MHz LPC3131FET180 180 MHz/ 90 MHz LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 0.8 mm pitch Total High-speed 10-bit SRAM USB ADC ...

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... ADC EVENT ROUTER RANDOM NUMBER GENERATOR APB slave group 1 TIMER 0/1/2/3 PWM I2C0 I2C1 (1) LPC3131 only Fig 1. LPC3130/3131 block diagram LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers JTAG LPC3130/3131 DMA HIGH-SPEED CONTROLLER master master MULTILAYER AHB MATRIX slave slave slave ...

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... ADC10B_GPA2 14 Row C 1 EBI_D_7 2 5 mGPIO9 6 9 VDDI 10 13 VDDE_IOC 14 Row D 1 EBI_D_5 2 5 VDDE_IOC 6 9 VSSE_IOC 10 13 BUF_TCK 14 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers ball A1 LPC3130/3131 index area ...

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... Row M 1 USB_ID 2 5 VDDE_IOB 6 9 VDDE_IOB 10 13 mI2STX_DATA0 14 Row N 1 USB_GNDA 2 5 mLCD_DB_8 6 9 mLCD_RW_WR 10 13 mUART_CTS_N 14 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers …continued Pin Symbol EBI_D_4 3 mNAND_RYBN0 7 VDDA12 11 I2STX_BCK1 - EBI_D_1 3 SCAN_TDO 11 I2SRX_BCK1 - EBI_D_0 3 I2STX_WS1 11 I2SRX_DATA1 - EBI_NRAS_BLOUT_1 3 GPIO12 ...

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... ADC10B_GPA0 B14 ADC10B_GPA1 A14 ADC10B_GPA2 B13 ADC10B_GPA3 C14 USB HS 2.0 OTG USB_VBUS L2 USB_ID M1 USB_RREF J5 USB_DP P2 USB_DM N2 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers …continued Pin Symbol USB_DP 3 mLCD_DB_3 7 TMS 11 mUART_RTS_N - Table 10 for pin function selection of multiplexed pins. Digital Application Pin Cell ...

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... I2C_SCL0 D10 [3] I2C_SDA1 E12 [3] I2C_SCL1 E13 Serial Peripheral Interface [3] SPI_CS_OUT0 A7 [3] SPI_SCK A8 [3] SPI_MISO C8 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Table 10 for pin function selection of multiplexed pins. Digital Application Pin Cell I/O function state Type level after [1] reset SUP1 Supply ...

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... C13; D5; D7; E8; G12; L10; VDDE_ESD K11 VSSE_IOA C3; C4; E4; F4; H4; K3 VSSE_IOB M3; M4; M6; M8 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Table 10 for pin function selection of multiplexed pins. Digital Application Pin Cell I/O function state Type level after [1] reset SUP3 DIO I DIO4 ...

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... L5 [3] mLCD_DB_10 K7 [3] mLCD_DB_11 N4 [3] mLCD_DB_12 K5 [3] mLCD_DB_13 P4 [3] mLCD_DB_14 P3 [3] mLCD_DB_15 N3 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Table 10 for pin function selection of multiplexed pins. Digital Application Pin Cell I/O function state Type level after [1] reset Ground - PG1 SUP8 ...

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... GPIO13 J12 GPIO14 J14 GPIO15 J13 GPIO16 J11 GPIO17 K12 GPIO18 K14 GPIO19 H11 GPIO20 K13 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Table 10 for pin function selection of multiplexed pins. Digital Application Pin Cell I/O function state Type level after [1] reset ...

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... The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and SPI_CS_OUT2) LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Table 10 for pin function selection of multiplexed pins ...

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... CS1 vddco CS2 vddi PS1 vdde3v3 PS2 vdde CG1 vssco CG2 vssis PG1 vsse LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Related supply pins VDDI, VDDA12, USB_VDDA12_PLL, Digital core supply VDDE_IOC, ADC10B_VDDA33, USB_VDDA33_DRV, USB_VDDA33, VDDE_IOA USB_VBUS VDDE_IOB Section 6.26.3.) Function Description Digital Input/Output Bidirectional 3.3 V ...

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... The processor core clock can be set equal to the AHB bus clock integer number times the AHB bus clock. The processor can be switched dynamically between these settings. • ARM stall support. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Rev. 1 — 9 February 2009 LPC3130/3131 © ...

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... ISROM reserved 96 kB ISRAM1 96 kB ISRAM0 reserved shadow area 0 GB (1) LPC3131 only. Fig 3. LPC3130/3131 memory map LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 0xFFFF FFFF 0x8000 0000 0x7000 0800 0x7000 0000 APB4 domain 0x6000 1000 0x6000 0000 0x4000 0000 ...

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... Wear leveling support with 516 byte mode. • Software controlled command and address transfers to support wide range of flash devices. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers shows a block diagram of the NAND flash controller module. The heart of the AHB MULTILAYER MATRIX ...

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... Static memory features include: – asynchronous page mode read – programmable wait states – bus turnaround delay – output enable and write enable delays LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Rev. 1 — 9 February 2009 LPC3130/3131 total codeword © ...

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... Contains pre-defined MMU table (16 kB) for simple systems. The boot ROM determines the boot mode based on reset state of GPIO0, GPIO1, and GPIO2 pins. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Memory map of the external SRAM/SDRAM memory modules Maximum address space ...

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... Supports SDIO version 1.10. • Supports MMCplus, MMCmobile and MMCmicro cards based on MMC 4.1. • Supports SDHC memory cards. • CRC generation and checking. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers LPC3130/3131 boot modes GPIO0 GPIO1 GPIO2 Description Boots from NAND flash. If proper image is not found, boot ROM will switch to DFU boot mode ...

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... Memory to memory: – Memory can be copied from the source address to the destination address with a specified length, while incrementing the address for both the source and destination. Memory to peripheral: LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Rev. 1 — 9 February 2009 LPC3130/3131 © ...

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... Visibility of the interrupt’s request state before masking. • Support for nesting of interrupt service routines. • Interrupts routed to IRQ and to FIQ are vectored. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Peripherals that support DMA access Rev. 1 — 9 February 2009 LPC3130/3131 ...

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... Multiple masters can have access to different slaves at the same time. Figure 5 AHB masters and slaves are numbered according to their AHB port number. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers gives an overview of the multi-layer AHB configuration in the LPC3130/3131. ...

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... ARM DMA 926EJ-S masters 0 1 AHB MULTILAYER MATRIX = master/slave connection supported by matrix (1) LPC3131 only. Fig 5. LPC3130/3131 multi-layer AHB matrix connections This module has the following features: LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers USB-OTG AHB MASTER 2 3 asynchronous slaves bridge 0 ...

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... CGU belongs to one of the domains. Each clock domain is fed by a single base clock that originates from one of the available clock sources. Within a clock domain, fractional dividers are available to divide the base clock to a lower frequency. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Rev. 1 — ...

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... Fractional dividers support clock stretching to obtain a (near duty cycle output clock. • Register interface to reset all modules under software control. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 6.19). For example, all clocks (including the ARM /bus clocks) are off and Section 6 ...

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... Watchdog counter can be reset by a periodical software trigger. • After a reset, a register will indicate whether a reset has occurred because of a watchdog generated reset. • Watchdog timer can also be used as a normal timer (output m0). LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers subdomain clocks BASE SYSTEM ...

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... The maximum conversion rate is 400 ksample/s for 10 bit resolution and 1500 ksample/s for 2 bit resolution. • Single A/D conversion scan mode and continuous A/D conversion scan mode. • Power-down mode. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers m0 EVENT ROUTER WDT APB ...

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... Module can be used to generate a system wake-up from suspend mode. Remark: All pins that can be used as GPIO are connected to the event router (see Figure 8). Note that they can be used to trigger events when in normal functional mode or in GPIO mode. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers interrupt 0 interrupt 1 ...

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... Frame error, overrun error and break detection. • Automatic hardware flow control. • Independent control of transmit, receive, line status, data set interrupts, and FIFOs. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Rev. 1 — 9 February 2009 LPC3130/3131 © NXP B.V. 2009. All rights reserved. ...

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... Contains an 16 byte FIFO for sending control and data information to the LCD controller. • Supports maskable interrupts. • Supports DMA transfers. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Rev. 1 — 9 February 2009 LPC3130/3131 © NXP B.V. 2009. All rights reserved ...

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... I2STX_0 output and the PCM interface. The pin interface multiplexing is subdivided into five categories: storage, video, audio, NAND flash, and UART related pin multiplexing. Each category supports several modes, which can be selected by programming the corresponding registers in the SysCReg. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 2 C master/slave interfaces ...

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... LCD_DB_11 mLCD_DB_12 LCD_DB_12 mLCD_DB_13 LCD_DB_13 mLCD_DB_14 LCD_DB_14 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Description Signal EBI_NSTCS_0 LCD_CSB — LCD chip select for external LCD controller. EBI_NSTCS_0 — EBI static memory chip select 0. EBI_NSTCS_1 LCD_DB_1 — LCD bidirectional data line 1. ...

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... I2STX_BCK0 mI2STX_WS0 I2STX_WS0 mI2STX_CLK0 I2STX_CLK0 UART related pin multiplexing mUART_CTS_N UART_CTS_N mUART_RTS_N UART_RTS_N LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers …continued Description Signal EBI_A_15 LCD_DB_15 — LCD bidirectional data line 15. EBI_A_15 — EBI address line 15. MCI_CLK GPIO5 — General Purpose I/O pin 5. ...

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... NAND_RYBN[0:3] INTERFACE control EBI_NCAS_BLOUT_0 3 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE Fig 9. Diagram of LCD and MPMC multiplexing Figure 9 signals are visible. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Figure 9 gives a high level overview of the modules in the chip that are control (ALE, CLE) NAND 2 FLASH address ...

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... LCD display. This module has the following features: • Supports Pulse Width Modulation (PWM) with software controlled duty cycle. • Supports Pulse Density Modulation (PDM) with software controlled pulse density. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Section 6.6). Figure 9 the EBI (NAND fl ...

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... Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right samples) to reduce busload. • Provides maskable interrupts for audio status: FIFO underrun/overrun/full/ half_full/not empty for left and right channel separately. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 2 S standard. ...

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... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. [2] Dependent on package type. [3] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers [1] Conditions Min VDDE_IOC = 3 ...

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... I LOW-level input IL current I HIGH-level input IH current I I/O latch-up current latch LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Conditions Min NAND flash controller 1.65 pads (SUP4) and LCD interface (SUP8); 1.8 V mode NAND flash controller 2.5 pads (SUP4) and LCD interface (SUP8); 2.8 V ...

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... V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I OFF-state output OZ current LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Conditions Min inputs with pull-up SUP4/SUP8; <tbd> 1.8 V mode SUP4/SUP8; <tbd> 2.8 V mode SUP3 <tbd> inputs with pull-down SUP4/SUP8 ...

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... V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI USB V common-mode input IC voltage V differential input i(dif) voltage LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Conditions Min V = VDDE_IOx - C VDDE_IOx - C VDDE_IOx ...

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... ADC T and the ideal transfer curve. See [9] See Figure 11. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Conditions = 3.3 V. DD(ADC the difference between the actual step width and the ideal step width. See ...

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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 10. ADC characteristics LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers (2) (5) (4) (3) 1 LSB (ideal) 1018 ...

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... NXP Semiconductors Fig 11. Suggested 10-bit ADC interface LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers LPC31XX tbd k ADC SAMPLE tbd pF tbd pF V SSA Rev. 1 — 9 February 2009 LPC3130/3131 R vsi AD10B_GPA[0:3] V EXT 002aae136 © NXP B.V. 2009. All rights reserved ...

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... Fig 12. LCD timing (Intel 8080 mode) LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Dynamic characteristics: LCD controller in Intel 8080 mode = +85 C, unless otherwise specified; V amb ...

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... Fig 13. LCD timing (Motorola 6800 mode) LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Dynamic characteristics: LCD controller in Motorola 6800 mode = +85 C, unless otherwise specified; V amb ...

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... Fig 14. LCD timing (serial mode) LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Dynamic characteristics: LCD controller serial mode = +85 C, unless otherwise specified; V amb Conditions clock cycle time ...

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... Refer to the LPC3130/3131 user manual for the programming of WAITWEN and HCLK. [5] Refer to the LPC3130/3131 user manual for the programming of WAITWR and HCLK. [6] (WAITWD WAITWEN + min at 60 MHz. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers = 1.8 V and 2.8 V (SUP8). DD(IO) Conditions Min Typ ...

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... NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_DQM_0_NOE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 EBI_D_[15:0] Fig 15. External memory read access to static memory LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers t CSLAV t OELAV t OELOEH t CSLOEL t BLSLAV t BLSLBLSH t CSLBLSL Rev. 1 — 9 February 2009 LPC3130/3131 t CSHOEH t OEHANV t CSHBLSH t BLSHANV t h(DQ) t su(DQ) 002aae161 © ...

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... NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_D_[15:0] EBI_NWE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 Fig 16. External memory write access to static memory LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers t CSLAV t CSLDV t WELWEH t CSLWEL t WELDV t BLSLBLSH t CSLBLSL Rev. 1 — 9 February 2009 LPC3130/3131 t BLSHANV t WEHANV t WEHDNV t BLSHDNV 002aae162 © NXP B.V. 2009. All rights reserved. ...

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... QZ high-impedance time [1] Parameters are valid over operating temperature range unless otherwise specified. [2] All values valid for pads set to high slew rate. VDDE_IOA = VDDE_IOB = 1.8 [ 1/T oper CLCL LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers = 1.8 V and 2.8 V (SUP8). DD(IO) Conditions Min [ ...

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... NXP Semiconductors T t CHCX EBI_CLKOUT EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] EBI_CKE is HIGH. Fig 17. SDRAM burst read timing LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers CLCL t CLCX t t d(o) h(o) READ NOP t d(o) t h(A) BANK, t su(D) COLUMN CAS LATENCY = 2 Rev. 1 — 9 February 2009 ...

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T CLCL t CHCX EBI_CLKOUT EBI_CKE EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] Fig 18. SDRAM bank activate and write timing t CLCX t d( d(o) h(o) ACTIVE t h(A) BANK, ROW t d(AV) t h(o) WRITE ...

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... [1] T HCLK [2] See registers NandTiming1 and NandTiming2 in the LPC3130/3131 user manual . Fig 19. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Dynamic characteristics of the NAND flash memory controller Parameter RE HIGH hold time RE pulse width WE HIGH hold time WE pulse width CLE set-up time ...

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... SPIDH t SPIQV t SPIOH Remark: Note that the signal names SCK, MISO, and MOSI correspond to signals on pins SPI_SCK, SPI_MOSI, and SPI_MISO in the following SPI timing diagrams. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Conditions input; on pin FFAST_IN output; on pin FFAST_OUT Dynamic characteristics of SPI pins ...

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... NXP Semiconductors Fig 20. Fig 21. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI MISO DATA VALID SPI master timing (CPHA = 1) SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI DATA VALID MISO SPI master timing (CPHA = 0) Rev. 1 — ...

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... NXP Semiconductors Fig 22. Fig 23. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID t SPIQV MISO DATA VALID SPI slave timing (CPHA = 1) SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID t SPIQV MISO DATA VALID SPI slave timing (CPHA = 0) Rev. 1 — ...

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... Remark: Note that the signal names SCK, MISO, and MOSI correspond to signals on pins SPI_SCK, SPI_MOSI, and SPI_MISO in the following SPI timing diagram. shifting edges SCK MOSI MISO Fig 24. MISO line set-up time in SSI Master mode LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers [1] Conditions Min ...

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... I2STX_BCK0 or I2STX_BCK1 I2STX_DATA0 or I2STX_DATA1 I2STX_WS0 or I2STX_WS1 Fig 25. I LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 2 S-bus interface pins Conditions [1] on pin I2STX_DATAx [1] on pin I2STX_WSx [1] on pin I2SRX_DATAx [1] on pin I2SRX_WSx ...

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... Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [3] Bus capacitance C in pF, from 400 pF. b LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers T cy(clk ...

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... JR1 t receiver jitter for paired transitions JR2 t EOP width at receiver EOPR1 t EOP width at receiver EOPR2 [1] Characterized but not implemented as production test. Guaranteed by design. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers LOW HD;STA HIGH SU ...

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... Fig 28. Differential data-to-EOP transition skew and EOP width 9.10 10-bit ADC Table 26: Dynamic characteristics: 10-bit ADC Symbol Parameter f sampling frequency s t conversion time conv LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers crossover point crossover point differential data to SE0/EOP skew PERIOD FDEOP ...

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Application information Table 27. LCD panel connections TFBGA pin # Pin name K8 mLCD_CSB/EBI_nSTCS0 L8 mLCD_E_RD/EBI_CKE P8 mLCD_RS/EBI_NDYCS N9 mLCD_RW_WR/EBI_DQM1 N8 mLCD_DB0/EBI_CLKOUT P9 mLCD_DB1/EBI_NSTCS1 N6 mLCD_DB2/EBI_A2 P6 mLCD_DB3/EBI_A3 N7 mLCD_DB3/EBI_A4 P7 mLCD_DB5/EBI_A5 K6 mLCD_DB6/EBI_A6 P5 mLCD_DB3/EBI_A7 N5 mLCD_DB3/EBI_A8 L5 ...

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... NXP Semiconductors 11. Marking Table 28. Line A LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers LPC3130/3131 Marking Marking Description LPC3130/3131 BASIC_TYPE Rev. 1 — 9 February 2009 LPC3130/3131 © NXP B.V. 2009. All rights reserved ...

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... DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 mm nom 1.06 0.35 0.71 min 0.95 0.30 0.65 OUTLINE VERSION IEC SOT570-3 Fig 29. LPC3130/3131 TFBGA180 package outline LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 1 1 ...

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... JTAG LSB MCI MCU MMC MPMC OTG PCM PHY PLL PWM LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture ARM Peripheral Bus Advanced Transport Architecture Bus Interface Unit ...

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... SDR SE0 SIR SPI SSI SysCReg TAP TDO UART USB UTMI WDT LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Abbreviations …continued Description Random Number Generator Read-Only Memory Secure Digital Secure Digital High Capacity Secure Digital Input Output Single Data Rate ...

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... NXP Semiconductors 14. Revision history Table 30: Revision history Document ID Release date LPC3130_3131_1 20090209 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Data sheet status Change notice Preliminary data sheet - Rev. 1 — 9 February 2009 LPC3130/3131 Supersedes - © NXP B.V. 2009. All rights reserved ...

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... NXP Semiconductors product can reasonably be expected 16. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers [3] Definition This document contains data from the objective specification for product development. ...

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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 9 February 2009 Document identifier: LPC3130_3131_1 ...

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