74lvx74 STMicroelectronics, 74lvx74 Datasheet

no-image

74lvx74

Manufacturer Part Number
74lvx74
Description
Low Voltage Cmos Dual D-type Flip Flop With Preset And Clear 5 V Tolerant Inputs
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVX74
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74lvx74M
Manufacturer:
UTC
Quantity:
499
Part Number:
74lvx74MSCX
Manufacturer:
TOSHIBA
Quantity:
15 745
Part Number:
74lvx74MTCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74lvx74MTR
Manufacturer:
ST
0
Part Number:
74lvx74MX
Manufacturer:
AMP
Quantity:
4 823
Part Number:
74lvx74MX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74lvx74SJX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74lvx74TTR
Manufacturer:
ST
0
DESCRIPTION
The 74LVX74 is a low voltage CMOS DUAL
D-TYPE FLIP-FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
HIGH SPEED:
f
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL:
V
LOW POWER DISSIPATION:
I
LOW NOISE:
V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
MAX
CC
PLH
OH
IL
OLP
CC
=0.8V, V
= 2 A (MAX.) at T
| = I
(OPR) = 2V to 3.6V (1.2V Data Retention)
= 145MHz (TYP.) at V
= 0.3V (TYP.) at V
t
PHL
OL
WITH PRESET AND CLEAR (5V TOLERANT INPUTS)
= 4mA (MIN)
IH
=2V AT V
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
A
CC
=25°C
CC
=3V
CC
= 3.3V
= 3.3V
2
MOS
Table 1: Order Codes
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse. CLR and PR are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
PACKAGE
TSSOP
SOP
SOP
Rev. 3
74LVX74
74LVX74MTR
74LVX74TTR
TSSOP
T & R
1/13

Related parts for 74lvx74

74lvx74 Summary of contents

Page 1

... PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS DESCRIPTION The 74LVX74 is a low voltage CMOS DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C technology ideal for low power, battery operated and low noise 3 ...

Page 2

... Figure 2: Input Equivalent Circuit Table 3: Truth Table INPUTS CLR Don’t Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 Table 2: Pin Description PIN N° ...

Page 3

... Value -55 to 125 0 to 100 Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min. 1.5 1.5 2.0 2.0 2.4 2.4 0.5 0.5 0.8 0.8 0.8 0.8 2.0 1.9 1.9 3.0 2.9 2.9 2.48 2.4 0.0 0.1 0.1 0.0 0.1 0.1 0.36 0.44 0 74LVX74 Unit °C °C Unit °C ns/V Unit Max. V 0.5 0.8 V 0.8 V 0.1 0 3/13 ...

Page 4

... Table 7: Dynamic Switching Characteristics Symbol Parameter V Dynamic Low Voltage OLP Quiet Output (note OLV V Dynamic High Voltage IHD Input (note Dynamic Low Voltage ILD Input (note Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. ...

Page 5

... pulse generator (typically OUT Test Condition (V) Min. 3 MHz 3.3 IN Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min CC(opr 74LVX74 Unit Max (per circuit 5/13 ...

Page 6

... Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform - Recovery Time (f=1MHz; 50% duty cycle) 6/13 ...

Page 7

... Figure 7: Waveform - Propagation Delays, Minimum Pulse Width (f=1MHz; 50% duty cycle) Figure 8: Waveform - Minimum Pulse Width 74LVX74 7/13 ...

Page 8

... DIM. MIN. A 1.35 A1 0.1 A2 1.10 B 0.33 C 0.19 D 8. 5.8 h 0.25 L 0.4 k 0° ddd 8/13 SO-14 MECHANICAL DATA mm. TYP MAX. 1.75 0.25 1.65 0.51 0.25 8.75 4.0 1.27 6.2 0.50 1.27 8° 0.100 inch MIN. TYP. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 0.228 0.010 0.016 0° 0016019D MAX. 0.069 0.010 0.065 0.020 0.010 0.344 0.157 ...

Page 9

... PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 5 5.1 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. 74LVX74 inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.0089 0.193 0.197 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ 0.018 0.024 0080337D MAX. 0.047 0.006 0.041 0.012 ...

Page 10

... DIM. MIN 12 2.1 Po 3.9 P 7.9 10/13 Tape & Reel SO-14 MECHANICAL DATA mm. TYP MAX. 330 13.2 22.4 6.6 9.2 2.3 4.1 8.1 inch MIN. TYP. 12.992 0.504 0.795 2.362 0.252 0.354 0.082 0.153 0.311 MAX. 0.519 0.882 0.260 0.362 0.090 0.161 0.319 ...

Page 11

... Tape & Reel TSSOP14 MECHANICAL DATA DIM. MIN 12 6.7 Bo 5.3 Ko 1.6 Po 3.9 P 7.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 6.9 0.264 5.5 0.209 1.8 0.063 4.1 0.153 8.1 0.311 74LVX74 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.272 0.217 0.071 0.161 0.319 11/13 ...

Page 12

... Table 10: Revision History Date Revision 27-Aug-2004 3 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies www.st.com 74LVX74 13/13 ...

Related keywords