74LVX573MTR STMicroelectronics, 74LVX573MTR Datasheet

IC DTYPE LATCH 3-ST OCTAL 20SOP

74LVX573MTR

Manufacturer Part Number
74LVX573MTR
Description
IC DTYPE LATCH 3-ST OCTAL 20SOP
Manufacturer
STMicroelectronics
Series
74LVXr
Datasheet

Specifications of 74LVX573MTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
8.4ns
Current - Output High, Low
4mA, 4mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-SOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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74LVX573MTR
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DESCRIPTION
The 74LVX573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
HIGH SPEED:
t
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
LOW POWER DISSIPATION:
I
LOW NOISE:
V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
PD
CC
PLH
OH
IL
OLP
CC
=6.4ns (TYP.) at V
= 0.8V, V
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 3.6V (1.2V Data Retention)
= 0.3V (TYP.) at V
t
PHL
OL
= 4 mA (MIN) at V
IH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
= 2V at V
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
CC
A
=25°C
CC
CC
= 3.3V
=3.3V
=3V
CC
= 3V
2
MOS
Table 1: Order Codes
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
SOP
74LVX573
Rev. 4
74LVX573MTR
74LVX573TTR
TSSOP
T & R
1/13

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74LVX573MTR Summary of contents

Page 1

... CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVX573 SOP TSSOP PACKAGE T & R SOP 74LVX573MTR TSSOP 74LVX573TTR Rev. 4 1/13 ...

Page 2

Figure 2: Input Equivalent Circuit Table 3: Truth Table Don’t Care Z : High Impedance * : Q Outputs are Latched at the time when the LE INPUT is taken low logic ...

Page 3

Table 4: Absolute Maximum Ratings Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

Table 7: Dynamic Switching Characteristics Symbol Parameter V Dynamic Low OLP Voltage Quiet V OLV Output (note 1, 2) Dynamic High V Voltage Input IHD (note 1, 3) Dynamic Low V Voltage Input ILD (note Worst ...

Page 5

Table 9: Capacitive Characteristics Symbol Parameter C Input Capacitance IN C Output OUT Capacitance C Power Dissipation PD Capacitance (note defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating ...

Page 6

Figure 5: Waveform - Propagation Delays, Le Minimun Pulse Width Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) 6/13 ...

Page 7

Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle) 74LVX573 7/13 ...

Page 8

DIM. MIN. A 2.35 A1 0.1 B 0.33 C 0.23 D 12. 10.00 h 0.25 L 0.4 k 0° ddd 8/13 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 1.27 10.65 ...

Page 9

TSSOP20 MECHANICAL DATA DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 ...

Page 10

DIM. MIN 12 10.8 Bo 13.2 Ko 3.1 Po 3.9 P 11.9 10/13 Tape & Reel SO-20 MECHANICAL DATA mm. TYP MAX. 330 13.2 30.4 11 13.4 3.3 4.1 12.1 inch ...

Page 11

Tape & Reel TSSOP20 MECHANICAL DATA DIM. MIN 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 0.272 1.9 ...

Page 12

Table 10: Revision History Date Revision 27-Aug-2004 4 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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