cy62126dv30 Cypress Semiconductor Corporation., cy62126dv30 Datasheet

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cy62126dv30

Manufacturer Part Number
cy62126dv30
Description
1-mbit 64k X 16 Static Ram
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Note:
Cypress Semiconductor Corporation
Document #: 38-05230 Rev. *H
Features
Functional Description
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• Very high speed
• Temperature Ranges
• Wide voltage range
• Pin compatible with CY62126BV
• Ultra-low active power
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 48-ball VFBGA and
— 2.2V - 3.6V
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f
44-pin TSOP Type II packages
— 55 ns
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
Logic Block Diagram
A
A
A
A
A
A
A
A
A
A
A
10
3
1
0
9
8
7
6
5
4
2
[1]
Max
COLUMN DECODER
DATA IN DRIVERS
(55 ns speed)
198 Champion Court
RAM Array
64K x 16
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH). The input/output pins (I/O
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
1-Mbit (64K x 16) Static RAM
15
San Jose
). If Byte High Enable (BHE) is LOW, then data
8
through I/O
,
CA 95134-1709
0
I/O
I/O
to I/O
CY62126DV30 MoBL
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
7
7
15
. If Byte High Enable (BHE) is
15
0
Revised July 18, 2006
) is written into the location
0
through A
through I/O
0
15
through I/O
).
15
8
408-943-2600
to I/O
) are placed
15
. See
®
7
), is
) in
®
0
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cy62126dv30 Summary of contents

Page 1

... Easy memory expansion with CE and OE features • Automatic power-down when deselected • Available in Pb-free and non Pb-free 48-ball VFBGA and 44-pin TSOP Type II packages [1] Functional Description The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features Logic Block Diagram ...

Page 2

... I I/O 5 I CY62126DV30 MoBL Power Dissipation (mA) CC Standby, I SB2 (µA) Max [2] [2] Typ. Max. Typ. Max. 1 1 1.5 Top View ...

Page 3

... L CC − 0.75V for pulse durations less than 20 ns. IH(max.) CC from & V must be stable at V CC(min) CC CC(min) ® CY62126DV30 MoBL [6] ................................ −0. 0. −40°C to +85°C 2.2V to 3.6V −40°C to +125°C 2.2V to 3.6V CY62126DV30-55 [5] Min. Typ. Max. Unit 2 ...

Page 4

... CE > − 0. > V < 0. DATA RETENTION MODE CC(min) V > 1 CDR >100 µ CC(min.) CY62126DV30 MoBL Max. Unit = CC(typ TSOP VFBGA Unit 55 76 °C °C/W ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns ...

Page 5

... V CC(typ.) is less than less than HZCE LZCE HZBE LZBE HZOE , BHE and/or BLE = ® CY62126DV30 MoBL CY62126DV30-55 Min. Max. Unit ...

Page 6

... WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #: 38-05230 Rev. *H [14, 15 OHA DOE DATA VALID 50 ® CY62126DV30 MoBL DATA VALID HZCE t HZOE t HZBE HIGH IMPEDANCE Page [+] Feedback ...

Page 7

... During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05230 Rev SCE PWE DATA VALID SCE PWE VALID DATA IN ® CY62126DV30 MoBL Page [+] Feedback ...

Page 8

... Write Cycle No. 4 (BHE/BLE-controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O NOTE 19 Document #: 38-05230 Rev. *H [17, 18 SCE PWE t SD DATA VALID IN [17, 18 SCE PWE t SD DATA VALID IN ® CY62126DV30 MoBL LZWE Page [+] Feedback ...

Page 9

... Fine-Pitch Ball Grid Array ( mm) 48-ball Fine-Pitch Ball Grid Array ( mm) (Pb-free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-free) 51-85150 48-ball Fine-Pitch Ball Grid Array ( mm) (Pb-free) 51-85087 44-pin TSOP II (Pb-free) ® CY62126DV30 MoBL Mode Power Standby ( Active ( Active (I ...

Page 10

... 6.00±0.10 SEATING PLANE C Document #: 38-05230 Rev. *H 48-ball VFBGA ( mm) (51-85150) A ® CY62126DV30 MoBL BOTTOM VIEW A1 CORNER Ø0. Ø0. Ø0.30±0.05(48X 1.875 ...

Page 11

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62126DV30 MoBL 44-pin TSOP II (51-85087) ® ...

Page 12

... Changed 44-pin TSOP-II package name from Z44 to ZS44 Added Temperature Ranges in the Features Section on Page # 1 Added Automotive Product Information for CY62126DV30-L for 55 ns Added I and I values for Automotive range of CY62126DV30-L for 55 ns SB1 SB2 Added Automotive Information for I CCDR Added Pb-free packages in the ordering information ...

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