CY7C1345-100AC Cypress Semiconductor Corporation., CY7C1345-100AC Datasheet
CY7C1345-100AC
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CY7C1345-100AC Summary of contents
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... Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Functional Description The CY7C1345 is a 3.3V, 128K by 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access ...
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... DDQ V 21 SSQ BYTE3 SSQ V 27 DDQ 100-Lead TQFP 100-Pin TQFP CY7C1345 2 CY7C1345 DDQ 76 V SSQ BYTE1 SSQ V 70 DDQ 69 ...
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... The outputs are automatically [3:0] three-stated when a Write cycle is detected. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 3 CY7C1345 are also loaded into the burst [1:0] are also loaded into the burst [1:0] to select one of the 64K address loca- ...
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... Table 2. Counter Implementation for a Linear Sequence controls [15: All I/Os are First [31:24] Address and CE are all as CY7C1345 Description after clock rise. ADSP CDV is HIGH. 1 Second Third Address Address ...
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... CY7C1345 , ADSP, and ADSC must remain 2 3 after the ZZ input returns ZZREC ADV WE OE CLK L-H High L-H High L-H High L-H High ...
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... X X [5] DC Input Voltage ................................ –0. Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Ambient [6] Range Temperature + 0.5V Com’ + CY7C1345 ...
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... Max Device Deselected – 0. 0.3V, IN DDQ inputs switching MAX Max Device Deselected –0. 0.3V inputs static 7 CY7C1345 Min. Max. 2.4 1.7 0.4 0.7 1 0.3V –0.3 0 –30 5 –5 30 –5 5 –300 8.5-ns cycle, 117 MHz 350 10-ns cycle, 100 MHz ...
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... L (a) Test Conditions Min ZZ > > < 0.2V 2t CYC Test Conditions MHz 5.0V DD R1=317 3.3V OUTPUT 3.0V R2=351 5 pF GND INCLUDING JIG AND SCOPE (b) 8 CY7C1345 Max Unit CYC ns Max. Unit 4.0 pF 4.0 pF ALL INPUT PULSES 90% 90% 10% 10% 3.0 ns 3.0 ns ...
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... CHZ CLZ EOHZ EOLZ 11. At any given voltage and temperature, t (max) is less than t CHZ 12. This parameter is sampled and not 100% tested. [9] -117 Min. Max. Min. 8.5 10 3.0 4.0 3.0 4.0 2.0 2.0 0.5 0.5 7.5 2.0 2.0 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 3 [10,12] 3.5 [10,12 3.5 (min). CLZ 9 CY7C1345 -100 -90 -50 Max. Min. Max. Min. Max. Unit 11 20 4.5 4.5 4.5 4.5 2.0 2.0 0.5 0.5 8.0 8.5 11.0 2.0 2.0 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 3.5 3.5 3 3.5 3.5 3 3.5 3.5 3.5 ns ...
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... GW to define a write cycle (see Write Cycle Descriptions table). [3:0] 14. WDx stands for Write Data to Address X. B urst W rite ADSP ignored with CE inactive masks ADSP UNDEFINED = DON’T CARE 10 CY7C1345 Pipelined Write Unselected ADSC initiated write WD3 Unselected with CE 2 High-Z 3a ...
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... RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP DOH DON’T CARE = UNDEFINED 11 CY7C1345 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... ADSP ignored with CE HIGH 1 t EOHZ Q(B) D(C) (B+2) (B+1) (B+3) , and GW to define a write cycle (see Write Cycle Descriptions table). [1:0] and CE . All chip selects need to be active in order to select UNDEFINED = DON’T CARE 12 CY7C1345 ADH t CEH t CEH t WEH Q(D) (C+1) (C+2) (C+3) t DOH t CHZ ...
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... Data In/Out Out Out Out t CDV Back to Back Reads CYC CL CH WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out In t DOH Back to Back Writes = UNDEFINED = DON’T CARE 13 CY7C1345 WD2 WD3 WD4 t WEH D( CHZ ...
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... Timing Diagrams (continued) OE Switching Waveforms OE t EOHZ three-state I/Os t EOV t EOLZ 14 CY7C1345 ...
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... ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Note: 16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device. 17. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active CCZZ Three-state 15 CY7C1345 t ZZREC ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Name Package Type A101 100-Lead Thin Quad Flat Pack A101 100-Lead Thin Quad Flat Pack A101 100-Lead Thin Quad Flat Pack A101 100-Lead Thin Quad Flat Pack CY7C1345 Operating Range Commercial 51-85050-A ...