CYP15G0101 CYPRESS [Cypress Semiconductor], CYP15G0101 Datasheet
CYP15G0101
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CYP15G0101 Summary of contents
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... Note: 1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements. CYP(V)15G0101DXB refers to both devices. Cypress Semiconductor Corporation Document #: 38-02031 Rev. *I Single-channel HOTLink II™ Transceiver • Compatible with — ...
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... Single burst of 44 ones or 44 zeros. 3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol- lowed by 1 one. x10 x11 Phase Elasticity Align Buffer Buffer Decoder Encoder 8B/10B 8B/10B Framer Serializer Deserializer RX TX CYP15G0101DXB CYV15G0101DXB links. Some applications include on switches, routers, Page ...
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... RFMODE DECMODE RXRATE RXMODE RXCKSEL Document #: 38-02031 Rev. *I Bit-Rate Clock Transmit Mode 12 12 Latch Receive Signal Monitor Clock & Data Recovery PLL CYP15G0101DXB CYV15G0101DXB Character-Rate Clock Output Enable Latch BIST Enable Latch 8 3 Clock ¸2 Select Delay JTAG Boundary ...
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... GND GND GND GND GND GND GND GND GND GND TXD[3] TXD[6] TXCT[1] TXD[2] TXD[5] TXCT[0] RXCLK– TXD[1] TXD[4] TXD[7] RXCLK+ CYP15G0101DXB CYV15G0101DXB IN1+ V OUT1– CC [2] IN1– #NC OUT1+ SPDSEL PARCTL RFMODE GND TMS TRSTZ GND TCLK ...
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... Word Sync Sequence. When the transmit path is configured to select TXCLK to clock the input register (TXCKSEL = MID or HIGH), SCSEL is captured relative to TXCLK. = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges CYP15G0101DXB CYV15G0101DXB Page ...
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... TXCLKO+) is adjusted when TXRST = LOW and locked when TXRST = HIGH. Transmit Operating Mode. These inputs are interpreted to select one of nine operating modes of the transmit path. See Table 3 for a list of operating modes. (ground). The HIGH level is usually implemented by direct connection CYP15G0101DXB CYV15G0101DXB [3] (power). When CC ...
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... Receive Operating Mode. This input selects one of two RXST channel status reporting modes and is only interpreted when the Decoder is enabled (DECMODE ¹ LOW). See Table 12 for details. CYP15G0101DXB CYV15G0101DXB th the serial bit-rate) of the data being ...
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... Configuring RXCKSEL = HIGH is an invalid mode of operation. Serial Rate Select. This input specifies the operating bit-rate range of both transmit and receive PLLs. LOW = 195–400 MBd, MID = 400–800 MBd, HIGH = 800–1500 MBd. When SPDSEL=LOW, setting TXRATE=HIGH (Half-rate Reference Clock) is invalid. CYP15G0101DXB CYV15G0101DXB Page ...
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... OUTx± differential driver is powered down. When OELE returns LOW, the last values present on BOE[1:0] are captured in the internal Output Enable Latch. The specific mapping of BOE[1:0] signals to transmit output enables is listed in Table 8. If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable both outputs. CYP15G0101DXB CYV15G0101DXB Page ...
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... JTAG Test Clock. Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not selected. Test Data In. JTAG data input port. +3.3V power Signal and power ground for all internal circuits CYP15G0101DXB CYV15G0101DXB Page ...
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... LOW), only the TXD[7:0] data bits are checked for ODD PARCTL = HIGH with the Encoder enabled (or MID with the Encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are checked for ODD parity along with the TXOP bit. When PARCTL = LOW, parity checking is disabled. CYP15G0101DXB CYV15G0101DXB captured on both edges of ...
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... Transmit Shifter without modification. If parity checking is enabled (PARCTL ¹ LOW) and a parity error is detected, the 10-bit character is replaced with the 1001111000 pattern (+C0.7 character) regardless of the running disparity of the previous character. CYP15G0101DXB CYV15G0101DXB â â ESCON and FICON™, and Digital Video ...
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... TXCT[1:0] ¹ 00, the Word Sync Sequence is terminated, and a character representing the data and control bits is generated by the Encoder. This resets the Word Sync Sequence state machine such that it will start at the beginning of the sequence at the next occurrence of TXCT[1:0] = 11. CYP15G0101DXB CYV15G0101DXB Characters Generated Page ...
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... TXCT[1:0] inputs must both be sampled HIGH. The generation and operation of this Word Sync Sequence is the same as that documented for TX Mode 3. Document #: 38-02031 Rev. *I CYP15G0101DXB CYV15G0101DXB Transmit BIST The transmit channel contains an internal pattern generator that can be used to validate both device and link operation. ...
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... Table 10. The Analog Signal Detect monitor is active for the present Line Receiver, as selected by the INSEL input. When configured for local loop-back (LPEN = HIGH), the Analog Signal Detect Monitor is disabled. CYP15G0101DXB CYV15G0101DXB > 100 mV, or 200-mV DIFFS [10] [4] ...
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... LFIx should be HIGH. Receive Channel Enabled The CYP15G0101DXB receive channel can be enabled and disabled through the BOE[0] input, as controlled by the RXLE latch-enable signal. When RXLE = HIGH, the signal present on the BOE[0] input is passed through the Receive Channel Enable Latch to control the PLL and logic of the receive channel ...
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... Received Special Code characters are decoded using the Cypress column of Table 21. When DECMODE = HIGH, the 10-bit transmission characters are decoded using 20 and 21. Received Special Code characters are decoded using the Alternate column of Table 21. CYP15G0101DXB CYV15G0101DXB Page ...
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... Elasticity Buffer to be centered. The Elasticity Buffer may also be centered by a device reset operation initiated through the TRSTZ input. However, following such an event, the CYP(V)15G0101DXB will normally require a framing event before it will correctly decode characters. CYP15G0101DXB CYV15G0101DXB outputs are clocked relative ...
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... Note: 15. The RXOP output is also driven from the Output Register, but its interpretation is under the separate control of PARCTL. Document #: 38-02031 Rev. *I CYP15G0101DXB CYV15G0101DXB by sequencing the appropriate values on the BOE[1:0] inputs while the OELE and RXLE signals are raised and lowered. For ...
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... Parity Generation In addition to the eleven data and status bits that are presented, an RXOP parity output is also available. This allows the CYP15G0101DXB to support ODD parity gener- ation. To handle a wide range of system environments, the CYP15G0101DXB supports different forms of parity gener- ation (in addition to no parity). When the Decoder is enabled (DECMODE ¹ ...
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... Each 3-Level select input reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11, respectively. Description Type-B Status RESERVED CYP15G0101DXB CYV15G0101DXB Receive BIST Status (Receive BIST = Enabled) BIST Data Compare. Character compared correctly BIST Command Compare ...
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... Buffer Error No Compare Next Character BIST_COMMAND_COMPARE (001) Match Command Data or Command Data End-of-BIST State Yes, RXST = BIST_LAST_GOOD (010) No, RXST = BIST_ERROR (110) Figure 2. Receive BIST State Machine CYP15G0101DXB CYV15G0101DXB Receive BIST Detected LOW RX PLL Out of Lock RXST = RXST = BIST_DATA_COMPARE (000) No Page ...
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... Min. £ V £ Max. CC Min. £ V £ Max GND IN 100W differential load 150W differential load CYP15G0101DXB CYV15G0101DXB Ambient Temperature 0°C to +70°C –40°C to +85°C Min. Max. = Min. 2 –20 –100 –20 2 –0 ...
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... IHE 20% V 2.0V ILE V = 1.4V th £ 270 ps 0.8V £ Note [26] Over the Operating Range Description requirement still needs to be satisfied. DIFFS = = 3.3V, T 25°C, parallel outputs unloaded, RXCKSEL CC A CYP15G0101DXB CYV15G0101DXB Min. Max 450 900 560 1000 100 1200 V V – ...
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... When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW) could be used to clock the receive data out of the device. Document #: 38-02031 Rev. *I Over the Operating Range (continued) Description and t parameters. This means that at faster character rates the REFCLK duty cycle REFH REFL CYP15G0101DXB CYV15G0101DXB Min. Max. Unit 0.2 1 ...
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... 20) (when RXRATE = HIGH) or 1/(f * 10) (when RXRATE = LOW data is being received, or REF REF * 10) (when RXRATE = LOW) of the remote transmitter if data is being received operating link this is equivalent to t REF CYP15G0101DXB CYV15G0101DXB Min. 5100 SPDSEL = HIGH 50 SPDSEL = MID 100 SPDSEL = LOW ...
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... REFCLK t t REFH REFL t TREFDS t REFCLK t REFH Note 37 t TREFDS t TREFDH t REFCLK t REFH t TXCLKO t t TXCLKOD+ TXCLKOD– Note 38 = HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL CYP15G0101DXB CYV15G0101DXB t TXDH t TREFDH t REFL t TREFDS t TREFDH t REFL = Page LOW), data ...
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... REFH REFL 38 Note t TXCLKO t TXCLKOD– t REFCLK t t REFH REFL t RREFDA t REFDV+ t REFCDV+ t REFCLK t REFH t RREFDA t RREFDV t REFDV+ t REFCDV+ Note 40 CYP15G0101DXB CYV15G0101DXB t RREFDV t REFDV– t REFCDV– Note 40 t REFL t RREFDA t RREFDV t REFDV– t REFCDV– Page Note ...
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... RXCLK+ – RXCLK RXD[7:0], RXST[2:0], RXOP Receive Interface Read Timing RXCKSEL = MID RXRATE = HIGH RXCLK+ – RXCLK RXD[7:0], RXST[2:0], RXOP Document #: 38-02031 Rev. *I (continued) t RXCLKP t t RXCLKH RXCLKL t RXDV– t RXCLKP t RXCLKH t RXDV– CYP15G0101DXB CYV15G0101DXB t RXDV+ t RXCLKL t RXDV+ Page ...
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... RXD[1] LVTTL OUT G3 RXD[5] LVTTL OUT G4 GND GROUND G5 GND GROUND G6 GND GROUND G7 GND GROUND G8 TXOP LVTTL IN PU CYP15G0101DXB CYV15G0101DXB Ball ID Signal Name Signal Type G9 TXCLKO+ LVTTL OUT G10 TXCLKO– LVTTL OUT H1 RXD[0] LVTTL OUT H2 RXD[2] LVTTL OUT H3 RXD[6] LVTTL OUT ...
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... SC/D = LOW Special Character (c is set to K, and SC/D = HIGH). When c is set the decimal value of Document #: 38-02031 Rev. *I CYP15G0101DXB CYV15G0101DXB the binary number composed of the bits and A in that order, and the y is the decimal value of the binary number composed of the bits H, G, and F in that order ...
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... Character in which the error occurred. Table 19 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CYP15G0101DXB CYV15G0101DXB Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 ...
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... D1.3 011 00001 010010 0101 D2.3 011 00010 110001 0101 D3.3 011 00011 001010 0101 D4.3 011 00100 CYP15G0101DXB CYV15G0101DXB Current RD- Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 110001 1001 110001 1001 ...
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... D6.5 101 00110 000111 0010 D7.5 101 00111 000110 1101 D8.5 101 01000 100101 0010 D9.5 101 01001 CYP15G0101DXB CYV15G0101DXB Current RD- Current RD+ abcdei fghj abcdei fghj 101001 1100 101001 0011 011001 1100 011001 0011 111000 1100 000111 0011 111001 0011 000110 1100 ...
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... D11.7 111 01011 001101 0110 D12.7 111 01100 101100 0110 D13.7 111 01101 011100 0110 D14.7 111 01110 CYP15G0101DXB CYV15G0101DXB Current RD- Current RD+ abcdei fghj abcdei fghj 010101 1010 010101 1010 110100 1010 110100 1010 001101 1010 001101 1010 101100 1010 ...
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... D28.7 111 11100 010001 0110 D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYP15G0101DXB CYV15G0101DXB Current RD- Current RD+ abcdei fghj abcdei fghj 010111 0001 101000 1110 011011 0001 100100 1110 100011 0111 100011 0001 010011 0111 ...
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... C1.7 (CE1) 111 00001 111 00010 C2.7 (CE2) 111 00010 111 00100 C4.7 (CE4) 111 00100 = the specified value between 00 and FF). CYP15G0101DXB CYV15G0101DXB Bits Current RD- Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 001111 0011 ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Name Package Type BB100 100-ball Grid Array BB100 100-ball Grid Array BB100 100-ball Grid Array BB100 100-ball Grid Array CYP15G0101DXB CYV15G0101DXB Operating Range Commercial Industrial Commercial Industrial 51 -851 07-* B Page ...
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... Changed verbiage...Paragraph: Clock/Data Recovery Changed verbiage...Paragraph: Range Control Added Power-up Requirements POT Changed CYP15G0101DXB to CYP(V)15G0101DXB type corresponding to the Video-compliant parts Reduced the lower limit of the serial signaling rate from 200 Mbaud to 195 Mbaud and changed the associated specifications accordingly ...