EL4583 Intersil Corporation, EL4583 Datasheet
EL4583
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EL4583 Summary of contents
Page 1
... Outputs are: composite sync, vertical sync, filter, burst/back porch, horizontal, no signal detect, level, and odd/even output (in interlaced scan formats only). The EL4583 sync slice level is set to the mid-point between sync tip and the blanking level. This 50% point is determined by two internal sample and hold circuits that track sync tip and back porch levels ...
Page 2
... Vertical, Back porch and H are all active low Attenuation is a function See filter typical characteristics F 4. Vertical pulse width in absence of serrations on input signal 2 EL4583 = 25°C) Operating Temperature Range . . . . . . . . . . . . . . . . . -40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves +0.5V Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C ...
Page 3
... Analog This is the ground return for the signal paths in the chips, R Ground 3 EL4583 PIN FUNCTION connected between this input and ground determines the input filter characteristic. Increasing R F connected between pin 2 and ground determines the value of the minimum signal which triggers the LV MIN = 0 ...
Page 4
... Ambient Temperature (°C) 4 EL4583 Back Porch Clamp On Time vs R SET Level Out (Pin 9) vs Sync. Tip Amplitude Filter Attenuation 3.58MHz < 1000k , no signal detect output (pin 10) will default high at LV Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity ...
Page 5
... Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). f. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync. 5 EL4583 FIGURE 1. ...
Page 6
... EL4583 FIGURE 2. FIGURE 3. 6 ...
Page 7
... The corresponding current to restore the charge during sync will therefore be an order of 7 EL4583 FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL magnitude higher, and any resistance in series with C cause sync tip crushing. For this reason, the internal series ...
Page 8
... The half line pulses present in the input signal during vertical blanking are removed with an internal 2H eliminator circuit. The 2H 8 EL4583 eliminator initiates a time out period after a horizontal pulse is generated. The time out period is a function set by R ...
Page 9
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 EL4583 * Note: R must resistor SET ...