hi7191 Intersil Corporation, hi7191 Datasheet
hi7191
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hi7191 Summary of contents
Page 1
... The HI7190 and HI7191 are functionally the same device, but the HI7190 has tighter linearity specs. The HI7191 contains a serial I/O port and is compatible with most synchronous transfer formats including both the Motorola 6805/11 series SPI and Intel 8051 series SSR protocols ...
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... Pinout HI7191 (PDIP, SOIC) TOP VIEW 1 20 SCLK SDO 2 19 SDIO DRDY 5 16 DGND RLO RHI Functional Block Diagram AV DD TRANSDUCER BURN-OUT CURRENT PGIA V INHI V INLO V CM CLOCK GENERATOR OSC OSC ...
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... Typical Application Schematic +5V INPUT + INPUT - REFERENCE -5V 0.1μF 3 HI7191 10MHz 17 16 OSC OSC 4.7μF 0.1μ INHI 11 V INLO +2.5V V RHI 8 V RLO 4.7μF + AGND + 4.7μF 0.1μF 1 SCLK 3 SDIO DATA I/O 2 SDO DATA OUT 19 SYNC ...
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... Offset Calibration Limit Input Span DIGITAL INPUTS Input Logic High Voltage Input Logic Low Voltage HI7191 Thermal Information Thermal Resistance (Typical, Note 1) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150° Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C ...
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... REF RHI RLO. 10. These errors are on the order of the output noise shown in Table 1. 11. All inputs except OSC . The OSC input HI7191 = +5V -5V +5V +2.5V RHI = 10MHz, Bipolar Input Range Selected TEST CONDITIONS V = 0V, +5V IN ...
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... DRDY CS SCLK SDIO 1 6 HI7191 t PRE SCLK SCLKPW DSU SCLKPW t DHLD 1ST BIT FIGURE 1. DATA WRITE TO HI7191 1ST BIT t DV FIGURE 2. DATA READ FROM HI7191 5 6 FIGURE 3. DATA READ FROM HI7191 2ND BIT 2ND BIT t DRDY 7 8 FN4138.8 June 1, 2006 ...
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... Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial Interface using a 2-wire serial protocol Chip Select Input. Used to select the HI7191 for a serial data transfer cycle. This line can be tied to DGND. 5 DRDY An Active Low Interrupt indicating that a new data word is available for reading. ...
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... GAIN = 8 10 124.7 20.4 25 120.6 19.7 30 119.2 19.5 50 117.5 19.2 60 116.8 19.1 100 112.1 18.3 250 101.4 16.5 500 95.3 15.5 1000 83.1 13.5 2000 68.3 11.1 15494.7 8 HI7191 RMS NOISE (μV) (μV) HERTZ GAIN = 16 9.8 1.5 10 13.6 2.1 25 16.6 2.5 30 19.5 3.0 50 21.2 3.2 60 30.7 4.6 100 166.7 25.3 250 505.3 76.6 500 2101.8 318.5 1000 2221.4 2000 GAIN = 32 14.0 2.1 10 20.9 3.2 25 24.1 3 ...
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... The input signal is continuously sampled at the input to the HI7191 at a clock rate set by the oscillator frequency and the selected gain. This signal then passes through the sigma delta modulator (which includes the PGIA) and emerges as a pulse train whose code density contains the analog signal information ...
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... When the HI7191 is powered up it needs to be reset by pulling the RESET line low. The reset sets the internal registers of the HI7191 as shown in Table 2 and puts the part in the bipolar mode with a gain of 1 and offset binary coding. The filter notch of the digital filter is set at 30Hz while the I/O ...
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... HI7191. The PGIA has 4 selectable gain options which are implemented by multiple sampling of the input signal. Input signals can be gained up further to 16, 32 128. These higher gains are implemented in the digital section of the design to maintain a high signal to noise ratio through the front end amplifiers ...
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... See Figure 7 for an applications circuit. RATIOMETRIC CONFIGURATION LOAD CELL FIGURE 7. BURN-OUT CURRENT SOURCE CIRCUIT Digital Section Description A block diagram of the digital section of the HI7191 is shown in Figure 8. This section includes a low pass decimation filter, conversion controller, calibration logic, serial interface, and clock generator. MODULATOR CLOCK ...
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... HI7191. Clocking/Oscillators The master clock into the HI7191 can be supplied by either a crystal connected between the OSC shown in Figure 10A or a CMOS compatible clock signal connected to the OSC ...
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... Calibration Register. The user must apply the +Full Scale . From INLO voltage to the HI7191 analog inputs and allow the signal to settle before selecting this mode. After 4 conversion periods the DRDY line will activate signaling the calibration is complete and valid data is present in the Data Output Register ...
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... Reserved This mode is not used in the HI7191 and should not be selected. There is no internal detection logic to keep this condition from being selected and care should be taken not to assert this bit combination. ...
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... MCS51 and MCS96 family of microcontrollers, or other similar processors. SCLK - Serial clock. The serial clock pin is used to synchronize data to and from the HI7191 and to run the port state machines. In Synchronous External Clock Mode, SCLK is configured as an input, is supplied by the user, and can run 5MHz rate ...
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... CS SCLK Programming the Serial Interface It is useful to think of the HI7191 interface in terms of communication cycles. Each communication cycle happens in 2 phases. The first phase of every communication cycle is the writing of an instruction byte. The second phase is the data transfer as described by the instruction byte important to note that phase 2 of the communication cycle can be a single byte or a multi-byte transfer of data ...
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... Negative Full Scale Calibration Register. Write 2 1 LSB operations are done using the SDIO, CS and SCLK lines only, as all data is written into the HI7191 via the SDIO line even when using the 3-wire configuration. Figures 14 and 15 show typical write timing diagrams. ...
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... SDO FIGURE 16. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE LOW IR WRITE PHASE CS SCLK SDIO SDO FIGURE 17. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE HIGH 19 HI7191 15 D15 D18 D17 D16 DATA TRANSFER PHASE - TWO-BYTE WRITE ...
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... These bits determine the filter cutoff frequency, the position of the first notch and the data rate of the HI7191. The first notch of the filter is equal to the decimation rate and can be determined by the formula: 20 ...
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... MSB - Bit 1 is used to select whether a serial data transfer is MSB or LSB first. This bit allows the user to change the order that data can be transmitted or received by the HI7191. When this bit is cleared (MSB = 0) the MSB is the first bit in a serial data transfer. If set (MSB = 1), the LSB is 21 HI7191 the first bit transferred in the serial data stream ...
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... Self Calibration correction coefficient after a RESET has been applied. BYTE 2 MSB P23 P22 P21 P20 P19 22 HI7191 15 P15 O18 O17 O16 Negative Full Scale Calibration Register The Negative Full Scale Calibration Register is a 24-bit register containing the Negative Full Scale correction ...
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... METALLIZATION: Type: AlSiCu Å Thickness: Metal 2, 16k Å Metal 1, 6k Metallization Mask Layout CS DRDY DGND HI7191 SUBSTRATE POTENTIAL (POWERED UP PASSIVATION: Type: Sandwich Å Thickness: Nitride 8k Å USG 1k HI7191 OSC OSC DV AGND FN4138.8 June 1, 2006 ...
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... B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 24 HI7191 E20.3 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL E A2 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 HI7191 M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...