IDT71P72804 Integrated Device Technology, IDT71P72804 Datasheet
IDT71P72804
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IDT71P72804 Summary of contents
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... DATA (Note1) REG WRITE DRIVER ADD (Note2) REG (Note4) 18M MEMORY ARRAY CLK GEN SELECT OUTPUT CONTROL 1 IDT71P72804 IDT71P72604 TM Burst of two SRAMs are high-speed synchro- (Note4) (Note1 6109 drw 16 APRIL 2006 DSC-6109/0A ...
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Mb QDR II SRAM Burst of 2 The QDRII has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching ...
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Mb QDR II SRAM Burst of 2 Pin Definitions Symbol Pin Function Data input signals, sampled on the rising edge of K and K clocks during valid write operations Input D[X:0] ...
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Mb QDR II SRAM Burst of 2 Pin Definitions continued Symbol Pin Function DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings ...
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... Mb QDR II SRAM Burst of 2 Pin Configuration IDT71P72804 ( Doff V REF ...
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Mb QDR II SRAM Burst of 2 Pin Configuration IDT71P72604 (512K x 36 NC ...
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Mb QDR II SRAM Burst of 2 Absolute Maximum Ratings Symbol Rating V Supply Voltage on V with TERM DD Respect to GND V Supply Voltage on V with TERM DDQ ...
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Mb QDR II SRAM Burst of 2 Application Example Data In Data Out Address MEMORY CONTROLLER ...
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Mb QDR II SRAM Burst Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Parameter Symbol Input Leakage Current I IL Output Leakage Current I OL Operating ...
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Mb QDR II SRAM Burst of 2 Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (V = 1.8 ± 100mV 1.4V to 1.9V) DD DDQ Parameter ...
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Mb QDR II SRAM Burst Test Conditions (1) Parameter Symbol Core Power Supply Voltage V DD I/O Power Supply Voltage V DDQ Input High Level V IH Input ...
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Mb QDR II SRAM Burst Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges) Symbol Parameter Clock Parameters t Clock ...
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Mb QDR II SRAM Burst of 2 Timing Waveform of Combined Read and Write Cycles Read A0 Write A1 Read tKHKL tKLKH K R tIVKH tKHIX ...
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Mb QDR II SRAM Burst of 2 IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Ac- cess Port (TAP). The package pads ...
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Mb QDR II SRAM Burst of 2 Scan Register Definition Part Instruction Register 512Kx36 3 bits 1Mx18 3 bits Identification Register Definitions INSTRUCTION FIELD ALL DEVICES Revision Number (31:29) 0x0284 Device ...
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Mb QDR II SRAM Burst of 2 Boundary Scan Exit Order ORDER PIN ...
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Mb QDR II SRAM Burst of 2 JTAG DC Operating Conditions Parameter Symbol I/O Power Supply V DDQ Power Supply Voltage V DD Input High Level V IH Input Low Level ...
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Mb QDR II SRAM Burst of 2 JTAG AC Characteristics Parameter Symbol Min TCK Cycle Time t 50 CHCH TCK High Pulse Width t 20 CHCL TCK Low Pulse Width t ...
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Mb QDR II SRAM Burst of 2 Package Diagram Outline for 165-Ball Fine Pitch Grid Array Commercial and IndustrialTemperature Range 6.42 19 ...
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... Industrial (- + Restricted Hazardous Substance Device BQ 165 Fine Pitch Ball Grid Array (fBGA) 250 (1,2) Clock Frequency in MegaHertz 200 167 IDT71P72804 QDR II SRAM Burst of 2 IDT71P72604 512K x 36 QDR II SRAM Burst of 2 6109 drw 15 for Tech Support: sramhelp@idt.com 408-284-4532 ...
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 ( -Bit) 71P72604 (512K x 36-Bit QDR II SRAM Burst of 2 Revision History REVISION DATE PAGES 0 07/20/05 p.1-22 A 04/21/06 p.1-3,7-9 12,15,20 p. 7,11,17 ...