IDTCSPUA877A Integrated Device Technology, IDTCSPUA877A Datasheet

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IDTCSPUA877A

Manufacturer Part Number
IDTCSPUA877A
Description
1.8v Phase Locked Loop Differential 1 10 Sdram Clock Driver
Manufacturer
Integrated Device Technology
Datasheet

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IDTCSPUA877ABVG
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IDT
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IDTCSPUA877ABVG
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IDT, Integrated Device Technology Inc
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate)
• Operating frequency: 125MHz to 410MHz
• Stabilization time: <6us
• Very low skew: ≤ ≤ ≤ ≤ ≤ 40ps
• Very low jitter: ≤ ≤ ≤ ≤ ≤ 40ps
• 1.8V AV
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin VFQFPN packages
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.
COMMERCIAL TEMPERATURE RANGE
APPLICATIONS:
• Meets or exceeds JEDEC standard CUA877 for registered DDR2
• Along with SSTUA32864/66, DDR2 register, provides complete
FUNCTIONAL BLOCK DIAGRAM
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
c
SDRAM applications
clock driver
solution for DDR2 DIMMs
2006 Integrated Device Technology, Inc.
DD
and 1.8V V
DDQ
10K: - 100K:
FBIN
FBIN
CLK
CLK
OS
OE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
AV
DD
POWER
LOGIC
DOWN
MODE
TEST
PLL
AND
LD
1
DESCRIPTION:
to distribute one differential clock input pair(CLK, CLK ) to 10 differential
output pairs (Y
(FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization
of the outputs to the input reference is provided. OE, OS, and A
power-down and test mode logic. When A
off and bypassed for test mode purposes. When the differential clock inputs
(CLK, CLK) are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a clock driver current consumption of less
than 500µA.
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPUA877 ,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
+70°C). See Ordering Information for details.
LD, OS, or OE
LD or OE
PLL BYPASS
The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer
The CSPUA877A requires no external components and has been optimised
The CSPUA877A is available in Commercial Temperature Range (0°C to
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output
COMMERCIAL TEMPERATURE RANGE
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
VDD
IDTCSPUA877A
is grounded, the PLL is turned
OCTOBER 2006
VDD
DSC 6872/4
control the

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IDTCSPUA877A Summary of contents

Page 1

... See Ordering Information for details POWER OE DOWN AND LD, OS TEST OS MODE PLL BYPASS AV LOGIC DD LD PLL 1 COMMERCIAL TEMPERATURE RANGE IDTCSPUA877A , Y ) and one differential pair of feedback clock output [0:9] [0:9] is grounded, the PLL is turned VDD ...

Page 2

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION GND GND GND GND BALL VFBGA PAC K AGE LAYOUT Y Y FBIN FBIN FBOUT GND DDQ OE V DDQ ...

Page 3

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION, CONT DDQ CLK CLK 5 GND V 6 DDQ AGND DDQ 10 GND VFQFPN TOP VIEW RECOMMENDED OPERATING CONDITIONS Symbol DD (1) AV Supply Voltage V I/O Supply Voltage DDQ T Operating Free-Air Temperature ...

Page 4

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN DESCRIPTION (VFBGA) Pin Name AGND AV DD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND B2 - B5, C2, C5, H2, H5 D4, E2, E5, F2 DDQ A3, A4, B1, B6, C1, C6, K1, K2, K5, K6 [0:9] Y A1, A2, A5, A6, D1, D6, J1, J6, K3, K4 ...

Page 5

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER (1,2) FUNCTION TABLE INPUTS GND H X GND H X GND L H GND L L 1.8V (nom 1.8V (nom 1.8V (nom 1.8V (nom 1.8V (nom NOTES HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2. L(z) means the outputs are disabled to a LOW state, meeting the I 3 ...

Page 6

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C A Symbol Parameter V Input Clamp Voltage (All Inputs (2) Input LOW Voltage (OE, OS, CLK, CLK (2) Input HIGH Voltage (OE, OS, CLK, CLK) ...

Page 7

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER AC ELECTRICAL CHARACTERISTICS Symbol Description any Y any Y/Y DIS s Output Enable (OE) LR(I) Input Clock Slew Rate, measured single-ended LR(O) (4) s Output Clock Slew Rate, measured single-ended 160 to 410 OX (6) V Output Differential-Pair Cross-Voltage t Cycle-to-Cycle Period Jitter ...

Page 8

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS V DDQ CSPUA877A GND V /2 DDQ 2.97" 60 2.97" CSPUA877A V /2 DDQ 2.97" GND R = 120 60 2.97" GND Figure 1: Output Load Test Circuit 10 10pF V /2 DDQ R = 10: ...

Page 9

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT CLK CLK FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT t t cycle n cycle n jit(cc) cycle n cycle n+1 Cycle-to-Cycle jitter t t (Ø) (Ø)n ¦ (Ø)n (Ø Static Phase Offset ...

Page 10

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK t cycle jit(per) = cycle Period jitter ...

Page 11

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS OE Y Time Delay Between Output Enable (OE) and Clock Output (Y, Y) CLK CLK FBIN FBIN SSC OFF SSC ON t (Ø)DYN 50% V DDQ t EN 50% V DDQ 50 (Ø) t (Ø)DYN ...

Page 12

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS 80% Clock Inputs and Outputs SLR(I/O) BEAD VIA 1: 0603 CARD V DDQ 4.7uF 1206 GND VIA CARD NOTES: Place all decoupling capacitors as close to the CSPUA877A pins as possible. Use wide traces for A and AGND ...

Page 13

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER APPLICATION INFORMATION CLK R = 120: CLK R = 120 10pF Feedback path CLK R = 120: CLK FBIN R = 120 10pF FBIN Feedback path ~2.5" CSPUA877A 60: 8 more FBIN FBIN Clock Structure 1 ~2.5" CSPUA877A 60: 8 more Clock Structure 2 13 COMMERCIAL TEMPERATURE RANGE ~0.6" ...

Page 14

... IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER ORDERING INFORMATION IDTCSPUA XXXXX XX Package Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X Process Blank 0°C to +70°C (Commercial) BVG Very Fine Pitch Ball Grid Array - Green NLG Thermally Enhanced Plastic Very Fine Pitch Quad ...

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