ISL12025 Intersil Corporation, ISL12025 Datasheet
ISL12025
Related parts for ISL12025
ISL12025 Summary of contents
Page 1
... Data Sheet Real-Time Clock/Calendar with EEPROM The ISL12025 device is a low power real-time clock with timing and crystal compensation, clock/calender, 64-bit unique ID, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, CPU Supervisor and integrated 512 x 8-bit EEPROM Bytes per page format ...
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... The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated This input provides a backup supply voltage to the device. V BAT that the Power Supply ISL12025 OSC Compensation Timer Frequency 1Hz Oscillator Calendar Divider Logic Status Control/ Registers Registers Alarm ...
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... V Negative Slew rate DD SR- DD RESET OUTPUT V Output Low Voltage OL I Output Leakage Current LO 3 ISL12025 Thermal Information Thermal Resistance (Note SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10s +300°C = +2.7V to +5.5V 3.3V DD CONDITIONS CONDITIONS ...
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... Valid RESET RVALID DD Output V ISL12025-4.5A Reset Voltage RESET Level ISL12025 Reset Voltage Level ISL12025-3 Reset Voltage Level ISL12025-2.7A Reset Voltage Level ISL12025-2.7 Reset Voltage Level t Watchdog Timer Period WDO t Watchdog Timer Reset Time-Out RST Delay Interface Minimum Restart ...
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... Write by the user (it is the time from valid STOP condition at the end of Write WC sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle. 5 ISL12025 (Continued) CONDITIONS Measured at the 30 crossing ...
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... BIT OF LAST BYTE SDA t RSP SCL SDA RESET START NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (t V RESET PURST t R RESET 6 ISL12025 HIGH LOW t SU:DAT t HD:DAT FIGURE 1. BUS TIMING ACK STOP CONDITION FIGURE 2. WRITE CYCLE TIMING t RSP t > ...
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... V BAT BAT, 5.00 4.50 Vdd=5.5V 4.00 3.50 Vdd=3.3V 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -45 -35 -25 - Temperature FIGURE TEMPERATURE DD3 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 1.8 2.3 2.8 3.3 3.8 Vdd (V) FIGURE DD3 7 ISL12025 Temperature is +25°C unless otherwise specified 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 4.3 4.8 5.3 SBIB = 0 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0. -20 -40 -32 -28 -24 -20 -16 -12 4.3 4.8 5.3 DD SCL,SDA pullups = 0V BSW = 1.80 2.30 2.80 3.30 3 ...
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... X1, X2 The X1 and X2 pins are the input and output, respectively inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12025 to supply a timebase for the real-time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can ...
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... AM/PM format. When the ISL12025 powers up after the loss of both V and V , the clock will not DD BAT operate until at least one byte is written to the clock register. Reading the Real-Time Clock The RTC is read by initiating a Read command and specifying the address corresponding to the register of the Real-Time Clock ...
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... This bit set to “1” indicates that the device is operating from V , not read-only bit and is set/reset by BAT DD hardware (ISL12025 internally). Once the device begins operating from V , the device sets this bit to “0”. DD AL1, AL0: Alarm Bits These bits announce if either alarm 0 or alarm 1 match the real-time clock. If there is a match, the respective bit is set to ‘ ...
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... DWA0 EDW0 0005 YRA0 0004 MOA0 EMO0 0003 DTA0 EDT0 0002 HRA0 EHR0 0001 MNA0 EMN0 0000 SCA0 ESC0 11 ISL12025 TABLE 2. CLOCK/CONTROL MEMORY MAP BIT AL1 AL0 OSCF 0 0 Y2K21 Y2K20 Y2K13 Y22 Y21 Y20 ...
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... ATR0: Analog Trimming Register Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for 12 ISL12025 frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34ppm to +80ppm to the nominal frequency compensation ...
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... C Communications During Battery Backup and LVR Operation” on page 23 for important details. VTS2, VTS1, VTS0: V Select Bits RESET The ISL12025 is shipped with a default per the ordering information table. This register is RESET a non-volatile with no protection, therefore any writes to this location can change the default value from that marked on the package ...
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... Alarm's Seconds register is advised. 14 ISL12025 2. Other nonvolatile writes possible to do writes of less than an entire page, but the final byte must always be addresses 0000h through 0004h or 0008h though 000Ch to trigger a nonvolatile write. Writing to those blocks of 5 bytes sequentially, or individually, will trigger a nonvolatile write ...
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... BATHYS - Condition 2: V < TRIP ≈ 2.2V where V TRIP • Battery Backup Mode ( Normal Mode (V BAT The ISL12025 device will switch from the V mode when one of the following conditions occurs: - Condition 1: V > BAT BATHYS ≈ 50mV where V BATHYS - Condition 2: V > ...
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... The device supports the I C Protocol. SCL SDA 16 ISL12025 Clock and Data Data states on the SDA line can change only during SCL DURATION LOW. SDA state changes during SCL HIGH are reserved for disabled indicating start and stop conditions. See Figure 16. ...
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... When this R/W bit is a one, then a read operation is selected. A zero selects a write operation. See Figure 19. After loading the entire Slave Address Byte from the SDA bus, the ISL12025 compares the device identifier and device select bits with ‘1010111’ or ‘1101111’. Upon a correct STOP 8 ...
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... See the Device Operation section for more information. Page Write The ISL12025 has a page write operation initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is ...
Page 19
... To do this, the master issues a start condition followed by the Memory Array Slave Address Byte for a write or read operation (AEh or AFh). If the ISL12025 is still busy with the non-volatile write cycle, then no ACK will be returned. When the ISL12025 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation ...
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... In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 25. The ISL12025 then goes into Standby Power Mode after the stop and all bus activity will be ignored until a start is detected. This operation loads Issue STOP the new address into the address counter ...
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... TABLE 7. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC’S PARAMETER Frequency Frequency Tolerance Turnover Temperature Operating Temperature Range Parallel Load Capacitance Equivalent Series Resistance 21 ISL12025 DATA DATA K (2) (1) FIGURE 26 ...
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... RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Figure 27 shows a suggested layout for the ISL12025 or ISL12027 devices. FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8 22 ISL12025 TABLE 8 ...
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... TRIP Legacy Mode ISL12025 Mode. In actuality the V switching to battery backup, which will disable I to charge the ANYTIME the device goes into Battery Backup Mode. pin. Try to BAT Regardless of the battery voltage, the I to the V • Mode this mode the selection bits indicate switchover to battery backup at V communications in battery backup ...
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... POWER, V FIGURE 29. EXAMPLE RESET OPERATION IN MODE (3.0V) BAT V DD (2.63V) V RESET V TRIP (2.2V) tPURST RESET I BAT FIGURE 30. RESET OPERATION IN MODE D 24 ISL12025 BUS ACTIVE NOT CONNECTED) BAT BUS ACTIVE (BATTERY BACKUP MODE) (BATTERY BACKUP MODE) FN6371.1 October 18, 2006 ...
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... HEX INT ISL12025 After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds change from 59 to 00) by setting the AL0 bit in the status register to “1”. ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 26 ISL12025 M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 ISL12025 M8.173 8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE M ...