ISL12028 Intersil Corporation, ISL12028 Datasheet

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... Data Sheet Real Time Clock/Calendar with EEPROM The ISL12028 device is a low power real time clock with clock/calender, power-fail indicator, clock output and crystal compensation, two periodic or polled alarms (CMOS output), intelligent battery backup switching, CPU Supervisor, integrated 512 x 8 bit EEPROM configured in 16 Byte per page ...

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... ISL12028IBAZ 12028IBAZ ISL12028IV27Z 12028IV27Z ISL12028IV27AZ 1202827AZ ISL12028IV30AZ 1202830AZ ISL12028IVZ 12028IVZ ISL12028IVAZ 12028IVAZ NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Tape & ...

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... BAT V supply fails. This pin should be tied to ground if not used Power Supply 10, N.C. No Internal Connection ISL12028 DESCRIPTION threshold open drain active LOW output. TRIP supplies power to the device in the event that the BAT FN8233.3 April 17, 2006 ...

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... Output Leakage Current LO IRQ/F OUTPUT OUT, V Output High Voltage OH 4 ISL12028 Thermal Information Pins Thermal Resistance (Note) OUT 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10s 300°C = -40°C to +85°C, Typical values are at T ...

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... Valid RESET RVALID DD Output V ISL12028-4.5A Reset Voltage RESET Level ISL12028 Reset Voltage Level ISL12028-3 Reset Voltage Level ISL12028-2.7A Reset Voltage Level ISL12028-2.7 Reset Voltage Level t Watchdog Timer Period WDO t Watchdog Timer Reset Time-Out RST Delay Interface Minimum Restart ...

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... Write by the user the time from valid STOP condition at the end of Write WC sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 6 ISL12028 (Continued) CONDITIONS Measured at the 30 crossing ...

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... BIT OF LAST BYTE SDA t RSP SCL SDA RESET START Note: All inputs are ignored during the active reset period (t V RESET PURST t R RESET 7 ISL12028 HIGH LOW t SU:DAT t HD:DAT FIGURE 1. BUS TIMING ACK STOP CONDITION FIGURE 2. WRITE CYCLE TIMING t RSP t > ...

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... V BAT BAT, 5.00 4.50 Vdd=5.5V 4.00 3.50 Vdd=3.3V 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -45 -35 -25 - Temperature FIGURE TEMPERATURE DD3 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 1.8 2.3 2.8 3.3 3.8 Vdd (V) FIGURE DD3 8 ISL12028 Temperature is 25°C unless otherwise specified 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 4.3 4.8 5.3 SBIB = 0 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0. -20 -40 -32 -28 -24 -20 -16 -12 4.3 4.8 5.3 DD SCL,SDA pullups = 0V BSW = 1.80 2.30 2.80 3.30 3 ...

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... BAT The X1 and X2 pins are the input and output, respectively inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12028 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can ...

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... The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL12028 powers up after the loss of both V and V , the clock will not ...

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... RTCF: Real Time Clock Fail Bit This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL12028 internally) when the device powers up after having lost all power to the device (both V DD ...

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... MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. 12 ISL12028 according to the product variation, see device ordering information) BIT 6 5 ...

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... These are two output control bits. They select one of three divisions of the internal oscillator, that is applied to the IRQ/ F output pin. Table 4 shows the selection bits for this OUT output. When using this function, the Alarm output function is disabled. 13 ISL12028 TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS FO1 FO0 ...

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... ISL12028 VTS2, VTS1, VTS0: V (ATR = LOAD The ISL12028 is shipped with a default per the ordering information table. This register is RESET a non-volatile with no protection, therefore any writes to this location can change the default value from that marked on the package. If not changed with a non-volatile write, this value will not change over normal operating and storage conditions ...

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... Condition where V - Condition where V OUT • Battery Backup Mode (V The ISL12028 device will switch from the V when one of the following conditions occurs: - Condition where V - Condition where V There are two discrete situations that are possible when ...

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... The Legacy Mode power control conditions are illustrated in Figure 15. 16 ISL12028 V BAT FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE 2.2V 1.8V Power On Reset Application of power to the ISL12028 activates a Power BAT BATHYS Reset Circuit that pulls the RESET pin active. This signal provides several benefits. < V BAT TRIP - It prevents the system microprocessor from starting to operate with insufficient voltage ...

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... See Figure 17. SCL SDA SCL SDA 17 ISL12028 STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop ...

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... The last bit of the Slave Address Byte defines the operation to be performed. When this R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 19. After loading the entire Slave Address Byte from the SDA bus, the ISL12028 compares the device identifier and device DEVICE IDENTIFIER Array 1 0 ...

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... ISL12028 will not initiate an internal write cycle, and will continue to ACK commands. PAGE WRITE The ISL12028 has a page write operation initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is ...

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... To do this, the master issues a start condition followed by the Memory Array Slave Address Byte for a write or read operation (AEh or AFh). If the ISL12028 is still busy with the non-volatile write cycle then no ACK will be returned. When the ISL12028 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation ...

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... In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 25. The ISL12028 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter ...

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... TABLE 8. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC PARAMETER Frequency Frequency Tolerance Turnover Temperature Operating Temperature Range Parallel Load Capacitance Equivalent Series Resistance 22 ISL12028 DATA DATA K (1) (2) FIGURE 26 ...

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... These signals can couple into the oscillator circuit and produce double clocking or mis- clocking, seriously affecting the accuracy of the RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Below in Figure suggested layout for the ISL12029 or ISL12028 devices. R1 10k U1 XTAL1 ISL12028 32 ...

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... OUT oscilloscope (after enabling it with the control register, and using a pull-up resistor for the open-drain output). Alternatively, the ISL12028 IRQ/F OUT checked by setting an alarm for each minute. Using the pulse interrupt mode setting, the once-per-minute interrupt functions as an indication of proper oscillation ...

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... PMOS transistor and drain the battery. If that is the case then no DD RESET the designer should consider the ISL12028 device which has an open-drain output and avoids excessive current draw in battery backup. tPURST 2 I ...

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... After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the AL0 bit in the status register to “1” and also bringing the IRQ/F low. 26 ISL12028 tPURST Bus Active FIGURE 30. RESET OPERATION IN MODE D Example 2 – ...

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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 27 ISL12028 M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC M B ...

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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 28 ISL12028 M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC M ...