isl6556b Intersil Corporation, isl6556b Datasheet
isl6556b
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isl6556b Summary of contents
Page 1
... MOSFET driver IC. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting. The ISL6556B uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor. Ordering Information PART NUMBER TEMP. (° ...
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... Pinouts 32 LEAD QFN TOP VIEW VID3 1 2 VID2 3 VID1 4 VID0 5 VID12.5 6 OFS 7 TCOMP REF ISL6556B PWM4 23 ISEN4 22 ISEN2 21 PWM2 20 PWM1 19 ISEN1 18 GND 17 ISEN3 LEAD SOIC TOP VIEW FS OVP 1 28 PGOOD ...
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... RGND x1 VSEN OVP +200mV OFS OFFSET REF VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB TCOMP T 3 ISL6556B OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT-START CLOCK AND AND SAWTOOTH FAULT LOGIC GENERATOR ∑ ∑ ∑ ∑ ∑ E/A CHANNEL ...
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... VSEN OVP +200mV OFS OFFSET OFSOUT REF VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB TCOMP T 4 ISL6556B OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT-START CLOCK AND AND SAWTOOTH FAULT LOGIC GENERATOR ∑ ∑ ∑ ∑ ∑ E/A CHANNEL ...
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... Typical Application of ISL6556BCB +5V FB COMP VCC TCOMP VDIFF VSEN RGND REF PGOOD OVP ISL6556BCB PWM1 VID4 ISEN1 VID3 PWM2 VID2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 EN GND R T VID_PGOOD (BUFFERED) 5 ISL6556B +12V VCC BOOT UGATE PVCC PHASE HIP6601B ...
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... Typical Application of ISL6556BCR +5V COMP VCC FB OFSOUT VDIFF TCOMP VSEN RGND PGOOD REF OVP ISL6556BCR VID4 ISEN1 VID3 PWM1 VID2 PWM2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 GND ENLL +12V VID_PGOOD 6 ISL6556B +12V VCC BOOT UGATE PVCC PHASE ...
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... VCC tied to 12VDC thru 300Ω resistor VCC tied to 12VDC thru 300Ω resistor VCC Rising VCC Falling EN Rising Hysteresis Fault Reset ENLL = 5V (Note 5) (Note 5) VID = 010100 (ISL6556BCR Only) θ θ (°C/ 0°C to 105°C. J MIN TYP MAX ...
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... These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 6. During soft-start, VDAC rises from 0 to VID. The overvoltage trip level is the higher of 1.7V and VDAC + 0.2V. 8 ISL6556B TEST CONDITIONS Offset resistor connected to ground VCC = 5.00V, offset resistor connected to VCC R = 100kΩ ...
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... Driving EN below 1.14V will clear all fault states and prime the ISL6556 to soft-start when re-enabled. ENLL - This pin is implemented in QFN ISL6556B only. It’s a logic-level enable input for the controller. When asserted to a logic high, the ISL6556B is active depending on status of EN, the internal POR, VID inputs and pending fault states ...
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... The technical challenges associated with producing a single-phase converter which is both cost- effective and thermally viable have forced a change to the cost-saving approach of multi-phase. The ISL6556B controller helps simplifying the implementation by integrating vital functions and requiring minimal output components. The block ...
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... PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6556B is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1. The cycle time of the ...
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... DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6556B to include the combined tolerances of each of these elements. 12 ISL6556B The output of the error amplifier, V sawtooth waveform to generate the PWM signals ...
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... ISL6556B TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued) VID12.5 VDAC VID4 0 0.8375V 1 1 0.8500V 1 0 0.8625V 1 1 0.8750V 1 0 0.8875V 1 1 0.9000V 1 0 0.9125V 1 1 0.9250V 1 0 0.9375V ...
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... R DROOP ISEN Output-Voltage Offset Programming The ISL6556B allows the designer to accurately adjust the offset voltage. When a resistor connected between OFS OFS and VCC, the voltage across it is regulated to 2.0V. This causes a proportional current ( flow into OFS OFS is connected to ground, the voltage across it is regulated to 0 ...
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... Electrical Specifications). to DS(ON) (EQ. 10) FIGURE 8. POWER SEQUENCING USING THRESHOLD- 2. The ISL6556B features an enable input (EN) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the is typically between ISL6556B in shutdown until the voltage at EN rises above T 1 ...
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... The schematic in Figure 8 demonstrates sequencing the ISL6556B with the HIP660X family of Intersil MOSFET drivers, which require 12V bias. 3. (ISL6556BCR only) The voltage on ENLL must be logic high to enable the controller. This pin is typically connected to the VID_PGOOD. The ISL6556BBCR has this signal internally connected high. ...
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... VID plus 200mV. During soft-start, the overvoltage trip level is the higher of 1.7V or VID plus 200mV. Upon successful soft-start, the overvoltage trip level is 200mV above VID. Two actions are taken by the ISL6556B to protect the microprocessor load when an overvoltage condition occurs. ...
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... S d1 LOW 2 ISL6556B Thus the total maximum power dissipated in each lower MOSFET is approximated by the summation LOW,2 UPPER MOSFET POWER CALCULATION In addition to r MOSFET losses are due to currents conducted across the input voltage (V higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex ...
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... Case 1: and (OPTIONAL COMP DROOP - VDIFF LOAD-LINE REGULATED ISL6556B CIRCUIT , has already been chosen The target 0 1 ------------------- > 2π LC 2π ----------------------------------- - C FB 0.75V IN ...
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... Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). 20 ISL6556B At the beginning of the load transient, the output capacitors ) supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage ...
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... Input Supply Voltage Selection The VCC input of the ISL6556B can be connected either directly to a +5V supply or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used. A 300Ω resistor is suggested for limiting the current into the VCC pin to a worst-case maximum of approximately 25mA ...
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... DUTY CYCLE (V O FIGURE 17. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR SINGLE-PHASE CONVERTER 22 ISL6556B Layout Considerations O The following layout strategies are intended to minimize the O impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. These sections highlight some important practices which should not be overlooked during the layout process ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. 23 ISL6556B M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 ISL6556B L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...