LMK03001D National Semiconductor Corporation, LMK03001D Datasheet

LMK03001D

Manufacturer Part Number

LMK03001D

Description

Manufacturer

National Semiconductor Corporation

Datasheet

1.LMK03001D.pdf (30 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

LMK03001DISQE/NOPB

Manufacturer:

Quantity:

250

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Download datasheet (654Kb)

LMK03000 Family

Precision Clock Conditioner with Integrated VCO

General Description

The LMK03000 family of precision clock conditioners com-

bine the functions of jitter cleaning/reconditioning, multiplica-

tion, and distribution of a reference clock. The devices

integrate a Voltage Controlled Oscillator (VCO), a high per-

formance Integer-N Phase Locked Loop (PLL), a partially

integrated loop filter, and up to eight outputs in various LVDS

and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. In-

ternally, the VCO output goes through a VCO Divider to feed

the various clock distribution blocks.

Each clock distribution block includes a programmable di-

vider, a phase synchronization circuit, a programmable delay,

a clock output mux, and an LVDS or LVPECL output buffer.

This allows multiple integer-related and phase-adjusted

copies of the reference to be distributed to eight system com-

ponents.

The clock conditioners come in a 48-pin LLP package and are

footprint compatible with other clocking devices in the same

family.

Target Applications

■

System Diagram

TRI-STATE

Data Converter Clocking

Networking, SONET/SDH, DSLAM

Wireless Infrastructure

Medical

Test and Measurement

Military / Aerospace

is a registered trademark of National Semiconductor Corporation.

202114

Features

■

LMK03000C

LMK03000D

LMK03001C

LMK03001D

LMK03033C

LMK03000

LMK03001

LMK03033

Integrated VCO with very low phase noise floor

Integrated Integer-N PLL with outstanding normalized

phase noise contribution of -224 dBc/Hz

VCO divider values of 2 to 8 (all divides)

Channel divider values of 1, 2 to 510 (even divides)

LVDS and LVPECL clock outputs

Partially integrated loop filter

Dedicated divider and delay blocks on each clock output

Pin compatible family of clocking devices

3.15 to 3.45 V operation

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

200 fs RMS Clock generator performance (10 Hz to 20

MHz) with a clean input clock

Device

5 LVPECL

4 LVPECL

Outputs

3 LVDS

4 LVDS

Tuning Range

1185 - 1296

1470 - 1570

1843 - 2160

(MHz)

20211440

VCO

www.national.com

July 14, 2008

RMS Jitter

1200

400

800

400

800

500

800

(fs)

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