LTC1274 Linear Technology, LTC1274 Datasheet
LTC1274
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LTC1274 Summary of contents
Page 1
... In Sleep mode only 1 A will be drawn. A REFRDY signal is used to show the ADC is ready to sample after waking up from Sleep mode. The LTC1274 also provides the Sleep mode and REFRDY signal. The A/D converters convert 0V to 4.096V unipolar inputs from a single 5V supply or 2 ...
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... V + 0.3V DD Lead Temperature (Soldering, 10 sec)................. 300 C – 0.3V to 12V ORDER + PART NUMBER A IN – LTC1274CS REF AGND LTC1274IS REFRDY SLEEP NAP DGND T With Internal Reference (Notes 5, 6) CONDITIONS (Note 7) (Note OUT(REF) TOP VIEW ORDER PART NUMBER ...
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... 2.7V (LTC1277) LOGIC I = – – 200 4.75V 160 1.6mA O V =2.7V (LTC1277) LOGIC I = 160 1.6mA O LTC1274/LTC1277 MIN TYP MAX UNITS 0 to 4.096 V 2.048 MIN TYP MAX UNITS 72.5 dB – – 82 – – ...
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... LTC1274/LTC1277 U U DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER I High-Z Output Leakage D11 to D0 High-Z Output Capacitance D11 to D0 Output Source Current SOURCE I Output Sink Current SINK W U POWER REQUIRE E TS SYMBOL PARAMETER V Positive Supply Voltage (Notes 11, 12 Logic Supply (Notes 11,12) ...
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... Only) L (Note 10) (LTC1277 Only) (Note 10) (LTC1277 Only) Note 8: For LTC1274, bipolar offset is the offset voltage measured from = 25 C. – 0.5LSB when the output code flickers between 0000 0000 0000 and A 1111 1111 1111. For LTC1277, bipolar offset voltage is measured from – ...
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... Distortion vs Input Frequency 100kHz SAMPLE –20 –40 –60 2ND HARMONIC –80 THD 3RD HARMONIC –100 –120 10k 100k 1M 2M INPUT FREQUENCY (Hz) LTC1274/77 • TPC06 f = 100kHz SAMPLE fa = 9.54kHz fb = 9.79kHz 2fa – fb 3fa fa + 2fb 3fb LTC1274/77 • TPC08 Acquistion Time vs Source Impedance 3 ...
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... LOAD CURRENT (mA) Wake-Up Time vs C (Sleep Mode) REF 100k REF LTC1274/77 • TPC16 0 1 LT1274/77 • TPC13 ...
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... LTC1274/LTC1277 CTIO S RD (Pin 20): Read Input. This enables the output drivers when CS is low. CS (Pin 21): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. BUSY (Pin 21): The BUSY output shows the converter status low when a conversion is in progress. The rising Busy edge can be used to latch the conversion result ...
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... OL 6 1274/77 • TC01 LTC1274/LTC1277 (0V FOR UNIPOLAR MODE OR –5V FOR BIPOLAR MODE) COMPARATOR D11 • OUTPUT LATCHES • • D0 LTC1274 • (0V FOR UNIPOLAR MODE OR –5V FOR BIPOLAR MODE) COMPARATOR D7 • • OUTPUT LATCHES • • D1/9 • D0/8 LTC1277 • ...
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... A IN HOLD (LTC1277) input con- DYNAMIC PERFORMANCE The LTC1274/LTC1277 have excellent high speed sam- pling capability. FFT (Fast Fourier Transform) test tech- SAMPLE niques are used to test the ADCs’ frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output ...
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... INFORMATION using an FFT algorithm, the ADCs’ spectral content can be examined for frequencies outside the fundamental. Figures 2a and 2b show typical LTC1274 FFT plots. Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other fre- quency components at the A/D output ...
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... S/( becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The analog input of the LTC1274/LTC1277 is easy to drive. It draws only one small current spike while charg- ing the sample-and-hold capacitor at the end of conver- sion. During conversion the analog input draws only a small leakage current ...
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... The ADCs have an on-chip, temperature compensated, curvature corrected bandgap reference which is factory trimmed to 2.42V internally connected to the DAC and is available at Pin 2 (LTC1274) or Pin 3 (LTC1277) to provide up to 1mA current to an external load. For minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10 F tantalum in parallel with a 0 ...
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... Input signal leads to A and signal return leads from IN AGND (Pin 3 for LTC1274, Pin 4 for LTC1277) should be kept as short as possible to minimize input noise cou- pling. In applications where this is not possible a shielded cable between source and ADC is recommended. ...
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... Figure 11b can be used. For zero offset error, apply 0.50mV (i.e., 0.5LSB) at the input and adjust the offset trim until the LTC1274/LTC1277 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error, apply an analog input of 4.0945V (i.e., FS – ...
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... Timing and Control Conversion start and data read operations are controlled by three digital inputs in the LTC1274: CS, CONVST and RD. For the LTC1277 there are four digital inputs: CS, CONVST, RD and HBEN. Figure 12 shows the logic structure associated with these inputs for LTC1277. A falling edge on CONVST will start a conversion after the ADC has been selected (i ...
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... FLOP CLEAR CONV t 15 (SAMPLE DATA N DB11 TO DB0 DATA N DATA N DB7 TO DB0 DB11 TO DB8 ) LTC1274/LTC1277 CONVERSION START (RISING EDGE TRIGGER) 1274/77 • F12 DATA ( DB11 TO DB0 DATA N DATA ( DB7 TO DB0 DB7 TO DB0 LTC1274/77 • F13 17 ...
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... DB11 TO DB8 ) DATA N DB11 TO DB0 t 16 DATA N DATA N DB11 TO DB8 DB7 TO DB0 t 16 (SAMPLE DATA ( DB11 TO DB0 DATA N DATA ( DB7 TO DB0 DB7 TO DB0 LTC1274/77 • F14 (SAMPLE LTC1274/77 • F15 ...
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... ADC is in inactive periods. Both ADCs have a Sleep mode. To power down the ADCs, SLEEP (Pin 18 in LTC1274 or Pin 6 in LTC1277) needs to be driver low. When in Sleep mode, the LTC1274/LTC1277 will not start a conversion even though the CONVST goes low ...
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... F) REF ON OFF 0.598 – 0.614* (15.190 – 15.600 NOTE LT/GP 1195 10K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1995 ON LTC1274/77 • F18b 0.394 – 0.419 (10.007 – 10.643) ...