XC4006 XILINX [Xilinx, Inc], XC4006 Datasheet
XC4006
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XC4006 Summary of contents
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... For a detailed description of the device features, architec- ture, configuration methods and pin descriptions, see pages 2-9 through 2-45. XC4005 XC4006 XC4008 XC4010/10D 5,000 6,000 8,000 ...
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XC4000 Logic Cell Array Family Absolute Maximum Ratings Symbol Description V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum soldering ...
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... Speed Grade Symbol Device Max T XC4003 WAF XC4005 10.0 XC4006 11.0 XC4008 12.0 XC4010 13.0 XC4013 15.0 XC4025 21.0 T XC4003 12.0 WAFL XC4005 13.0 XC4006 14.0 XC4008 15.0 XC4010 16.0 XC4013 18.0 XC4025 24.0 T XC4003 WAO XC4005 10.0 XC4006 11.0 XC4008 12.0 XC4010 13.0 XC4013 15.0 XC4025 21.0 T XC4003 12.0 WAOL XC4005 13.0 XC4006 14.0 XC4008 15.0 XC4010 16.0 XC4013 18.0 XC4025 24.0 2- Max Max Units 9.0 8.0 5.0 9.0 6.0 10.0 7.0 11.0 8.0 12.0 9.0 14.0 11.0 19.0 17.0 11.0 7.0 12.0 8.0 13.0 9.0 14.0 10.0 15.0 11.0 17.0 13.0 23.0 20.0 9.0 8.0 6.0 9.0 7.0 10.0 8.0 11.0 9.0 12.0 10 ...
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... XC4025 20.0 T XC4003 9.3 IO2 XC4005 10.5 XC4006 11.1 XC4008 11.6 XC4010 12.2 XC4013 13.5 XC4025 23.5 T XC4003 10.7 ON XC4005 12.0 XC4006 12.6 XC4008 13.2 XC4010 13.8 XC4013 15.1 XC4025 23.0 T All devices 3.0 OFF T XC4003 24.0 PUS XC4005 26.0 XC4006 28.0 XC4008 30.0 XC4010 32.0 XC4013 36.0 XC4025 52.0 T XC4003 11.6 PUF XC4005 12.0 XC4006 13.0 XC4008 14.0 XC4010 15.0 XC4013 17.0 XC4025 24.0 2- Max Max Units 5.8 5.1 ns 6.0 5.5 ns 6.2 5.7 ns 6.6 6 ...
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... T for -4 Speed Grade PDLI XC4003 17.6 ns Pad to I1, I2 XC4005 17.9 ns via transparent XC4006 18.0 ns latch, with delay XC4008 18.3 ns XC4010 18.6 ns XC4013 19.3 ns XC4025 23.5 ns PRELIMINARY Speed Grade Symbol ...
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XC4000 Logic Cell Array Family IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived ...
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CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The ...
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XC4000 Logic Cell Array Family CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are ...
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CLB RAM Timing Characteristics ADDRESS WRITE WRITE ENABLE DATA IN READ X,Y OUTPUTS VALID READ, CLOCKING DATA INTO FLIP-FLOP CLOCK XQ,YQ OUTPUTS READ DURING WRITE WRITE ENABLE DATA IN (stable during WE) X,Y OUTPUTS DATA IN (changing during WE) X,Y ...
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XC4000 Logic Cell Array Family Pin Description PC84 PQ100 PG120 VCC 2 I/O (A8) 3 I/O (A9) 4 I/O – I/O – I/O (A10) 5 I/O (A11) 6 – – I/O (A12) 7 I/O (A13) 8 100 – – – ...
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Pin Bound Description PC84 PQ160 PQ208 PG156 Scan VCC 2 142 183 H3 I/O (A8) 3 143 184 H1 44 I/O (A9) 4 144 185 G1 47 I/O – 145 186 G2 50 I/O – 146 187 ...
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... GND Indicates unconnected package pins. † Contributes only one bit (.i) to the boundary scan register. XC4006 Pinouts PQ Boundary Pin 208 Description 183 - I/O 184 50 I/O 185 53 I/O 186 56 I/O 187 59 - 188 189* - I/O 190 62 I/O 191 ...
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... R11 92 I/O - T11 93 I/O (D5) 59 T10 94 I/O (CS0) 60 P10 I/O - R10 96 I I/O (D4 I 100 * Indicates unconnected package pins. XC4006 Pinouts (continued) PQ Boundary Pin 208 Description 79 - GND 80 247 I/O (D3) 81 250 I/O (RS) 82 253 I/O 83 256 I 259 I/O (D2) 87 262 I/O 88 265 I/O 89 268 I GND 91* ...
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XC4000 Logic Cell Array Family Pin 191 Description PC84 84 PQ160 PG191 PQ208 Scan Order 160 142 J4 I/O (A8) 3 143 J3 I/O (A9) 4 144 J2 I/O – 145 J1 I/O ...
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Pin 191 Description PC84 PQ160 PG191 PQ208 Scan Order 160 GND 43 61 K15 I K16 I K17 I/O – 64 K18 I/O – 65 L18 I/O – – L17 I/O – ...
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XC4000 Logic Cell Array Family Pin †† Description PC84 PQ160 PG191 PQ208 BG225 Scan Order 142 J4 183 I/O (A8) 3 143 J3 184 I/O (A9) 4 144 J2 185 I/O - 145 J1 186 I/O ...
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Pin Description PC84 PQ160 PG191 PQ208 BG225 Scan Order I M17 87 I N18 88 I P18 89 GND - 70 M16 90 I N17 91 I R18 92 ...
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XC4000 Logic Cell Array Family Pin PQ160 MQ208 PG223 BG225 PQ240 Scan Order Description 142 183 J4 I/O (A8) 143 184 J3 I/O (A9) 144 185 J2 I/O 145 186 J1 I/O 146 187 H1 I/O - ...
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XC4013/XC4013D Pinouts (continued) Pin PQ160 MQ208 PG223 BG225 PQ240 Scan Order Description GND 61 79 K15 R8 I K16 L8 I K17 M9 I K18 P9 I L18 R9 I ...
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XC4000 Logic Cell Array Family Pin Bound Description HQ208 HQ240 PG233 PG299 Scan VCC 183 212 J4 K1 I/O (A8) 184 213 I/O (A9) 185 214 I/O 186 215 I/O 187 ...
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Pin Description HQ208 HQ240 PG233 PG299 Scan GND 160 182 R3 X2 I/O (A0, WS) 161 183 PGCK4 (I/O, A1) 162 184 U1 V2 I/O 163 185 P3 R5 I/O 164 186 R2 T4 I/O (CS1, A2) ...
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... PC84 PQ100 VQ100 CB100 PG120 TQ144 PG156 PQ160 CB164 PG191 CB196 PQ208 MQ208 PG223 BG225 PQ240 MQ240 PG299 HQ304 CODE - XC4003 - - XC4005 - XC4006 - XC4008 - -10 XC4010 - XC4010D - ...