MAX3204EETT+T Maxim Integrated Products, MAX3204EETT+T Datasheet - Page 5

• Manufacturer Part Number: MAX3204EETT+T
• Description: IC ESD PROT ARRAY 6-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3204EETT+T

• Power (watts): 1.95W
• Polarization: 4 Channel Array - Unidirectional
• Mounting Type: Surface Mount
• Package / Case: 6-TDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Breakdown: -
• Voltage - Reverse Standoff (typ): -
• Lead Free Status / Rohs Status: Details
• Other names: MAX3204EETT+T; MAX3204EETT+TTR

During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 3). For example,
in a 15kV IEC-61000 Air-Gap Discharge ESD event,
the pulse current rises to approximately 45A in 1ns
(di/dt = 45 x 10
additional 450V to the clamp voltage. An inductance of
10nH represents approximately 0.5in of board trace.
Regardless of the device’s specified diode clamp volt-
age, a poor layout with parasitic inductance significantly
increases the effective clamp voltage at the protected
signal line.
A low-ESR 0.1μF capacitor must be used between V
and GND. This bypass capacitor absorbs the charge
transferred by an +8kV IEC-61000 Contact Discharge
ESD event.
Ideally, the supply rail (V
caused by a positive ESD strike without changing its
regulated value. In reality, all power supplies have an
effective output impedance on their positive rails. If a
power supply’s effective output impedance is 1Ω, then
by using V = I × R, the clamping voltage of V
es by the equation V
61000-4-2 ESD event generates a current spike of 24A,
so the clamping voltage increases by V
or V
bypassing increases the clamping voltage. A ceramic
chip capacitor mounted as close to the MAX3202E/
MAX3203E/MAX3204E/MAX3206E V
choice for this application. A bypass capacitor should
also be placed as close to the protected device as
possible.
ESD protection can be tested in various ways; the
MAX3202E/MAX3203E/MAX3204E/MAX3206E are
characterized for protection to the following limits:
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
Protection Arrays for High-Speed Data Interfaces
t
R
= 0.7ns to 1ns
C
= 24V. Again, a poor layout without proper
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
100%
90%
10%
I
9
). An inductance of only 10nH adds an
_______________________________________________________________________________________
30ns
C
= I
CC
±15kV ESD Protection
ESD
) would absorb the charge
60ns
x R
OUT
CC
. An +8kV IEC
C
pin is the best
= 24A × 1Ω,
C
increas-
t
CC
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
Figure 4 shows the Human Body Model, and Figure 5
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩ resistor.
Figure 4. Human Body ESD Test Model
Figure 5. Human Body Model Current Waveform
• ±15kV using the Human Body Model
• ±8kV using the Contact Discharge method speci-
• ±15kV using the IEC 61000-4-2 Air-Gap Discharge
AMPERES
VOLTAGE
SOURCE
HIGH-
fied in IEC 61000-4-2
method
DC
I
P
36.8%
100%
90%
10%
CHARGE-CURRENT-
LIMIT RESISTOR
0
0
1MΩ
R
t
C
100pF
RL
C s
STORAGE
CAPACITOR
CURRENT WAVEFORM
1.5kΩ
TIME
RESISTANCE
DISCHARGE
R
D
t
DL
I r
ESD Test Conditions
Human Body Model
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
DEVICE
UNDER
TEST
5