Manufactured under one or more of the following:
US Patents; 6,198,375/6,204,744/6,449,829/6,460,244.
Several foreign patents, and other patents pending.
Notes
(1)
(2)
(3)
(4)
(5)
Document Number: 34260
Revision: 20-Oct-09
± 20 % AT 100 kHz,
IHLP-2020CZ-11
STANDARD ELECTRICAL SPECIFICATIONS
DESCRIPTION
GLOBAL PART NUMBER
All test data is referenced to 25 °C ambient
Operating temperature range - 55 °C to + 125 °C
DC current (A) that will cause an approximate ΔT of 40 °C
DC current (A) that will cause L
The part temperature (ambient + temp. rise) should not exceed
125 °C under worst case operating conditions. Circuit design,
component placement, PWB trace size and thickness, airflow
and other cooling provisions all affect the part temperature. Part
temperature should be verified in the end application.
INDUCTANCE
I
0.25 V, 0 A
MODEL
PRODUCT FAMILY
(μH)
0.10
0.22
0.33
0.47
10.0
22.0
1.0
1.5
2.2
3.3
4.7
5.6
L
0
H
L
25 °C
122.1 131.9
250.0 260.0
INDUCTANCE VALUE
DCR
TYP.
(mΩ)
10.0
17.1
22.5
36.4
54.0
63.0
2.6
3.5
4.5
5.4
P
MAX.
25 °C
4.7 μH
(mΩ)
DCR
11.0
18.5
25.0
40.4
60.0
70.6
2.9
3.9
5.0
6.0
0
2
to drop approximately 20 %
CURRENT
DC TYP.
RATING
HEAT
21.00
21.00
16.50
14.00
10.00
(A)
7.50
6.75
5.50
4.50
4.25
2.75
1.90
For technical questions, contact:
0
Low Profile, High Current
(3)
INDUCTANCE TOLERANCE
2
SATURATION
SIZE
CURRENT
IHLP
DC TYP.
25.00
14.50
(A)
9.00
9.00
6.50
7.00
5.50
7.00
5.20
3.50
2.25
1.70
0
± 20 %
(4)
®
C
Inductors
Z
FEATURES
• Shielded construction
• Frequency range up to 1.0 MHz
• Lowest DCR/μH, in this package size
• Handles high transient current spikes without
• Ultra low buzz noise, due to composite construction
• Excellent temperature stability for inductance and
• Compliant to RoHS directive 2002/95/EC
APPLICATIONS
• PDA/notebook/desktop/server applications
• High current POL converters
• Low profile, high current power supplies
• Battery powered devices
• DC/DC converters in distributed power systems
• DC/DC converter for Field Programmable Gate Array
magnetics@vishay.com
0.204 ± 0.010
[5.18 ± 0.254]
DIMENSIONS in inches [millimeters]
saturation
saturation
(FPGA)
PACKAGE CODE
0.118
Max.
[3.0]
PACKAGE
E
CODE
0.040 ± 0.012
[1.02 ± 0.300]
ER
R
0.216 ± 0.010
[5.49 ± 0.250]
4
INDUCTANCE
JEDEC LEAD (Pb)-FREE STANDARD
VALUE
R
IHLP-2020CZ-11
[2.54 ± 0.254]
0.100 ± 0.010
7
[2.79]
0.110
Typical Pad Layout (Min.)
e3
TOL.
M
Vishay Dale
www.vishay.com
[5.99]
0.236
[2.16]
0.085
1
SERIES
1
1