PIC16F716-I/SO Microchip Technology, PIC16F716-I/SO Datasheet - Page 36

• Manufacturer Part Number: PIC16F716-I/SO
• Description: IC PIC MCU FLASH 2KX14 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F716-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 8-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3-DB16F716 - BOARD DAUGHTER ICEPIC3AC162054 - HEADER INTERFACE ICD2 16F716AC164010 - MODULE SKT PROMATEII DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F716
7.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1/P1A. An event is defined as:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit CCP1IF (PIR1<2>) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value will be lost.
FIGURE 7-1:
7.1.1
In Capture mode, the RB3/CCP1/P1A pin should be
configured as an input by setting the TRISB<3> bit.
7.1.2
Timer1
Synchronized Counter mode for the ECCP module to
use the capture feature. In Asynchronous Counter
mode, the capture operation may not work.
7.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS41206A-page 34
RB3/CCP1/P1A
Pin
Note:
Note:
Capture Mode
must
edge detect
Always
(CCP1M3:CCP1M0 = ‘0000’) between
changing from one capture mode to
another. This is necessary to reset the
internal capture counter.
CCP1 PIN CONFIGURATION
If the RB3/CCP1/P1A is configured as an
output, a write to PORTB can cause a
capture condition.
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
Q’s
Prescaler
1, 4, 16
and
CCP1CON<3:0>
be
Set flag bit CCP1IF
running
reset
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<2>)
the
Capture
Enable
in
CCPR1H
TMR1H
Timer
ECCP
mode
CCPR1L
TMR1L
module
Preliminary
or
7.1.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the ECCP module is
turned off, or the ECCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 7-1:
7.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1/P1A pin is
either:
• Driven High
• Driven Low
• Toggle output (high-to-low or low-to-high)
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Changing the ECCP mode to clear output on match
(CCP1M<3:0> = 1000) presets the CCP1 output latch
to the logic 1 level. Changing the ECCP mode to set
output on match (CCP1M<3:0> = 1001) presets the
CCP1 output latch to the logic 0 level.
CLRF
MOVLW
MOVWF CCP1CON
non-zero
Compare Mode
CCP1CON
NEW_CAPT_PS
ECCP PRESCALER
prescaler.
CHANGING BETWEEN
CAPTURE PRESCALERS
 2003 Microchip Technology Inc.
;Turn ECCP module off
;Load the W reg with
;the new prescaler
;mode value and ECCP ON
;Load CCP1CON with this
;value
Example 7-1
shows
the