PIC24F04KA201-I/SS Microchip Technology, PIC24F04KA201-I/SS Datasheet
PIC24F04KA201-I/SS
Specifications of PIC24F04KA201-I/SS
Related parts for PIC24F04KA201-I/SS
PIC24F04KA201-I/SS Summary of contents
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... XLP™ Technology © 2009 Microchip Technology Inc. PIC24F04KA201 Family 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary Data Sheet DS39937B ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24F04KA201 FAMILY Analog Features: • 10-Bit 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU): - Used for capacitance sensing - Compatible with mTouch™ ...
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... PIC24F04KA201 FAMILY Pin Diagrams (1) 14-Pin PDIP, TSSOP MCLR/V PGC2/AN0/V +/CN2/RA0 REF PGD2/AN1/V -/CN3/RA1 REF OSCI/CLKI/AN4/C1INB/CN30/RA2 OSCO/CLKO/AN5/C1INA/CN29/RA3 PGD3/SOSCI/AN2/C2INB/HLVDIN/CN1/RB4 PGC3/SOSCO/AN3/C2INA/T1CK/CN0/RA4 (1) 20-Pin PDIP, SSOP, SOIC MCLR/V PGC2/AN0/V REF PGD2/AN1/V REF AN2/C2INB/CN4/RB0 AN3/C2INA/CN5/RB1 U1RX/CN6/RB2 OSCI/CLKI/AN4/C1INB/CN30/RA2 OSCO/CLKO/AN5/C1INA/CN29/RA3 PGD3/SOSCI/CN1/RB4 PGC3/SOSCO/T1CK/CN0/RA4 All device pins have a maximum voltage of 3.6V and are not 5V tolerant. ...
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... Pin Diagrams (Continued) (1,2) 20-Pin QFN AN2/C2INB/CN4/RB0 AN3/C2INA/CN5/RB1 U1RX/U1BCLK/CN6/RB2 OSCI/CLKI/AN4/C1INB/CN30/RA2 OSCO/CLKO/AN5/C1INA/CN29/RA3 Connecting the bottom pad to Vss is recommended. Note 1: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY REFO/SS1/T2CK/T3CK/CN11/RB15 15 1 AN10/CV /SDI1/OCFA/C1OUT/INT1/CN12/RB14 2 14 ...
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... PIC24F04KA201 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 15 3.0 CPU ........................................................................................................................................................................................... 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory .............................................................................................................................................................. 43 6.0 Resets ........................................................................................................................................................................................ 51 7.0 Interrupt Controller ..................................................................................................................................................................... 57 8.0 Oscillator Configuration .............................................................................................................................................................. 81 9.0 Power-Saving Features .............................................................................................................................................................. 91 10.0 I/O Ports ..................................................................................................................................................................................... 99 11.0 Timer1 ..................................................................................................................................................................................... 101 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 5 ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... This document contains device-specific information for the following devices: • PIC24F04KA200 • PIC24F04KA201 The PIC24F04KA201 family introduces a new line of extreme low-power Microchip devices: a 16-bit micro- controller family with a broad peripheral feature set and enhanced computational performance. It also offers a new migration option for those high-performance appli- ...
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... Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. 1.4 Differences from PIC24F16KA102 Family The PIC24F04KA201 family architecture is very similar to that of the PIC24F16KA102 family. The PIC24F04KA201 family is a subset of the PIC24F16KA102 devices. The PIC24F16KA102 additional features: • ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC24F04KA201 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels ...
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... PIC24F04KA201 FAMILY FIGURE 1-1: PIC24F04KA201 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV and Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode and Control Power-up Timing OSCO/CLKO Generation Timer OSCI/CLKI Oscillator Start-up Timer FRC/LPRC ...
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... TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS Pin Number 14-Pin 20-Pin Function PDIP/TSSOP/ PDIP/SSOP/ SOIC SOIC AN0 2 2 AN1 3 3 AN2 6 4 AN3 7 5 AN4 4 7 AN5 5 8 AN10 11 17 AN11 — 16 AN12 — 15 U1BCLK 9 13 C1INA 5 8 C1INB 4 7 C1OUT 11 17 ...
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... PIC24F04KA201 FAMILY TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 14-Pin 20-Pin Function PDIP/TSSOP/ PDIP/SSOP/ SOIC SOIC HLVDIN 6 15 MCLR 1 1 OC1 10 14 OCFA 11 17 OSCI 4 7 OSCO 5 8 PGC2 2 2 PGD2 3 3 PGC3 7 10 PGD3 6 9 RA0 2 2 RA1 ...
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... TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 14-Pin 20-Pin Function PDIP/TSSOP/ PDIP/SSOP/ SOIC SOIC REF REF Schmitt Trigger input buffer, ANA = Analog level input/output, I Legend: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Input I/O 20-Pin Buffer QFN 17 P — ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 14 Preliminary © 2009 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY FIGURE 2- MCLR ( pins Key (all values are recommendations): )” ...
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... PIC24F04KA201 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...
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... Frequency (MHz) Data for Murata GRM21BF50J106ZE01 shown. Note: Measurements at 25° bias. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... PIC24F04KA201 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... PIC24F04KA201 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...
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... W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 15 0 Frame Pointer 0 Stack Pointer 0 SPLIM TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL ...
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... PIC24F04KA201 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 — — bit 15 (1) (1) R/W-0, HSC R/W-0, HSC R/W-0, HSC (2) (2) IPL2 IPL1 IPL0 bit 7 HSC = Hardware Settable/Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘ ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — ...
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... PIC24F04KA201 FAMILY 3.3.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24F04KA201 family of devices is displayed in Figure 4-1. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY ...
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... DEVICE CONFIGURATION WORDS Table 4-1 provides the addresses of the device Config- uration Words for the PIC24F04KA201 family. Their location in the memory map is displayed in Figure 4-1. Refer to Section 23.1 “Configuration Bits” for more information on device Configuration Words. TABLE 4-1: ...
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... Memory Using Program Space Visibility”). PIC24F04KA201 family devices implement a total of 768 words of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24F04KA201 FAMILY DEVICES MSB Address 0001h 07FFh 0801h ...
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... PIC24F04KA201 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory. For example, the core recog- ...
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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name — (1) (1) CNEN1 0060 CN14IE CN13IE CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 — CN14PUE (1) CN13PUE (1) CN12PUE CN11PUE CNPU2 ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-9: I C™ REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
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TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA 02C6 — — — — ...
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TABLE 4-15: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 4-17: DUAL COMPARATOR REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name — — — CMSTAT 0630 CMSIDL CVRCON 0632 — — — — CM1CON 0634 CON COE CPOL CLPWR CM2CON 0636 CON COE CPOL ...
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TABLE 4-20: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR PGMONLY NVMKEY 0766 — — — — — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ...
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... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of Note 1: the address is PSVPAG<0>. PSVPAG can have only one value (‘00’ to access program memory) on the PIC24F04KA201 family. 2: FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION ...
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... Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (byte select = 1). © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “ ...
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... PIC24F04KA201 FAMILY FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into an 8K word page (in PIC24F08KA1XX devices) and a 16K word page (in PIC24F16KA1XX devices) of the program space. This provides ...
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... Program Space PSVPAG The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Data Space 0 000000h 002BFEh PSV Area 800000h Preliminary 0000h Data EA<14:0> 8000h ...while the lower 15 bits ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 42 Preliminary © 2009 Microchip Technology Inc. ...
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... For more information on Flash programming, refer to the “PIC24F Family Reference Manual”, Section 4. “Program Memory” (DS39715). The PIC24F04KA201 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with V 1 ...
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... PIC24F04KA201 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions time and to program one row at a time also possible to program single words ...
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... Erase entire general memory block programming operations All other combinations of NVMOP<5:0> are no operation. Note 1: Available in ICSP™ mode only. Refer to device programming specification. 2: The address in the Table Pointer decides which rows will be erased. 3: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 PGMONLY — — R/W-0 ...
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... PIC24F04KA201 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is: 1. Read a row of program (32 instructions) and store in data RAM. 2. Update the program data in RAM with the desired new data ...
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... NVMCON = 0x4058; asm("DISI #5"); __builtin_write_NVM(); © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts for next 5 instructions ...
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... PIC24F04KA201 FAMILY EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV ...
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... MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; 2 NOPs required after setting Wait for the sequence to be completed ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 50 Preliminary © 2009 Microchip Technology Inc. ...
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... Uninitialized W Register © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets ...
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... PIC24F04KA201 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0, HS R/W-0, HS R/W-0 TRAPR IOPUWR SBOREN bit 15 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR SWDTEN bit Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit ...
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... Reset is chosen as shown in Table 6-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY (1) (CONTINUED) Setting Event TABLE 6-2: OSCILLATOR SELECTION vs. ...
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... PIC24F04KA201 FAMILY 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute ...
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... Brown-out Reset (BOR) The PIC24F04KA201 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the <BORV1:BORV0> and (BOREN<1:0>) Configura- tion bits (FPOR<6:5,1:0>). There are a total of four BOR configurations, which are provided in Table 6.3.1. ...
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... PIC24F04KA201 FAMILY 6.3.5 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • ...
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... Interrupt Vector 116 Interrupt Vector 117 Note 1: See Table 7-2 for the interrupt vector list. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR) ...
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... PIC24F04KA201 FAMILY TABLE 7-1: TRAP VECTOR DETAILS Vector Number IVT Address 0 000004h 1 000006h 2 000008h 3 00000Ah 4 00000Ch 5 00000Eh 6 000010h 7 000012h TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source ADC1 Conversion Done Comparator Event CTMU External Interrupt 0 External Interrupt 1 External Interrupt 2 I2C1 Master Event ...
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... Interrupt Control and Status Registers The PIC24F04KA201 family of devices implements a total of 23 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0, IFS1, IFS3 and IFS4 • IEC0, IEC1, IEC3 and IEC4 • IPC0 through IPC5, IPC7 and IPC15 through IPC19 • ...
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... PIC24F04KA201 FAMILY REGISTER 7-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0, HSC R/W-0, HSC R/W-0, HSC (2,3) (2,3) (2,3) IPL2 IPL1 IPL0 bit 7 HSC = Hardware Settable/Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘ ...
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... See Register 3-1 for the description of this bit, which is not dedicated to interrupt control functions. Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 2: Bit 2 is described in Section 3.0 “CPU”. Note: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — ...
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... PIC24F04KA201 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24F04KA201 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS U-0 R/W-0, HS NVMIF — AD1IF bit 15 R/W-0, HS U-0 U-0 T2IF — — bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NVMIF: NVM Interrupt Flag Status bit ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — R/W-0, HS ...
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... PIC24F04KA201 FAMILY REGISTER 7-7: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS — — CTMUIF bit 15 U-0 U-0 U-0 — — — bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
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... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 ...
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... PIC24F04KA201 FAMILY REGISTER 7-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Unimplemented: Read as ‘0’ bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... PIC24F04KA201 FAMILY REGISTER 7-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP2 T1IP1 bit 15 U-0 R/W-1 R/W-0 — IC1IP2 IC1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP< ...
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... T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 T2IP0 — — U-0 U-0 U-0 — ...
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... PIC24F04KA201 FAMILY REGISTER 7-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP2 U1RXIP1 bit 15 U-0 R/W-1 R/W-0 — SPF1IP2 SPF1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP< ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 NVMIP0 — — R/W-0 U-0 R/W-1 AD1IP0 — ...
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... PIC24F04KA201 FAMILY REGISTER 7-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP2 CNIP1 bit 15 U-0 R/W-1 R/W-0 — MI2C1P2 MI2C1P1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP< ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
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... PIC24F04KA201 FAMILY REGISTER 7-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP2 INT2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP< ...
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... U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 U-0 U1ERIP0 — ...
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... PIC24F04KA201 FAMILY REGISTER 7-19: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP< ...
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... VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
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... PIC24F04KA201 FAMILY 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
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... Oscillator Configuration, refer to the “PIC24F Family Reference Manual”, Section 38. “Oscillator with 500 kHz Low-Power FRC” (DS39726). The oscillator system for the PIC24F04KA201 family of devices has the following features: • A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. • ...
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... Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24F04KA201 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC< ...
Page 85
... Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The Clock Divider register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...
Page 86
... PIC24F04KA201 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1 Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...
Page 87
... Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Note 1: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 DOZEN ...
Page 88
... PIC24F04KA201 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
Page 89
... OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...
Page 90
... DS39937B-page 88 8.5 Reference Clock Output In addition to the CLKO output (F certain oscillator modes, the device clock in the PIC24F04KA201 family devices can also be configured to provide a reference clock output signal to a port pin. 9Ah to This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to application ...
Page 91
... Base clock value bit 7-0 Unimplemented: Read as ‘0’ The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Note 1: Sleep mode. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 ...
Page 92
... PIC24F04KA201 FAMILY NOTES: DS39937B-page 90 Preliminary © 2009 Microchip Technology Inc. ...
Page 93
... Family Reference Section 39. “Power-Saving Features with Deep Sleep” (DS39727). The PIC24F04KA201 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...
Page 94
... Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 9.2.4 DEEP SLEEP MODE In PIC24F04KA201 family devices, Deep Sleep mode is intended to provide the lowest levels of power consumption available, without requiring the use of external switches to completely remove all power from the device ...
Page 95
... Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON<0>). © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 9.2.4.4 I/O Pins During Deep Sleep During Deep Sleep, the general purpose I/O pins retain their previous states and the Secondary Oscillator (SOSC) will remain running, if enabled ...
Page 96
... PIC24F04KA201 FAMILY 9.2.4.5 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the ...
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... All register bits are reset only in the case of a POR event outside of Deep Sleep mode. Note 1: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this 2: re-arms POR. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY (1) U-0 U-0 U-0 — ...
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... PIC24F04KA201 FAMILY REGISTER 9-2: DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0, HS U-0 U-0 DSFLT — — bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
Page 99
... Enabling the automatic return to full-speed CPU operation on interrupts is enabled by set- ting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 9.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 98 Preliminary © 2009 Microchip Technology Inc. ...
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... For more information on the I/O Ports, refer to the “PIC24F Family Refer- ence Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24F04KA201 family devices do not support Peripheral Pin Select features. All of the device pins (except V ...
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... NOP. 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24F04KA201 family of devices to generate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are ...
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... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Figure 11-1 presents a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...
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... PIC24F04KA201 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 105
... Timer2 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY To configure Timer2/3 for 32-bit operation: 1. Set the T32 bit (T2CON<3> = 1). 2. ...
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... PIC24F04KA201 FAMILY FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 ADC Event Trigger Equal MSB Reset (1) Read TMR2 (1) Write TMR2 Data Bus<15:0> The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits Note 1: are respective to the T2CON register. ...
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... TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 12-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T3CK TGATE 1 Set T3IF 0 Reset ADC Event Trigger Equal © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 1x Gate Sync TMR2 Sync Comparator PR2 Sync 1x 01 ...
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... PIC24F04KA201 FAMILY REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T2CON<3> Starts 32-bit Timer2 Stops 32-bit Timer2/3 When T2CON< ...
Page 109
... External clock from the T3CK pin (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as ‘0’ When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer Note 1: functions are set through T2CON. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 (1) — — R/W-0 U-0 (1) ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 108 Preliminary © 2009 Microchip Technology Inc. ...
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... IC1CON System Bus © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The PIC24F04KA201 family devices have one input capture channel. The input capture module has multiple operating modes, which are selected via the IC1CON register. The operating modes include: • Capture timer value on every falling edge of input applied at the IC1 pin • ...
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... PIC24F04KA201 FAMILY 13.1 Input Capture Registers REGISTER 13-1: IC1CON: INPUT CAPTURE 1 CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 bit Hardware Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 113
... OC1IE bit. For further information on peripheral interrupts, refer to Section 7.0 “Interrupt Controller”. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘ ...
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... PIC24F04KA201 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode The following steps should be taken when configuring the output compare module for PWM operation: 1. Set the PWM period by writing to the selected Timer Period register (PRy). 2. Set the PWM duty cycle by writing to the OC1RS register. ...
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... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Based /2, Doze mode and PLL are disabled. Note 1: CY OSC © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY )/log 2) bits 10 2) bits 61 Hz 122 Hz 977 FFFFh 7FFFh 0FFFh 16 15 ...
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... PIC24F04KA201 FAMILY FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM (1) OC1RS (1) OC1R Comparator TMR Register Inputs from Time Bases Where ‘x’ is depicted, reference is made to the registers associated with the respective Output Compare Channel 1. Note 1: OCFA pin controls OC1 channel. 2: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the 3: time bases associated with the module ...
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... Initialize OC1 pin high, compare event forces OC1 pin low 001 = Initialize OC1 pin low, compare event forces OC1 pin high 000 = Output compare channel is disabled OCFA pin controls OC1 channel. Note 1: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — ...
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... PIC24F04KA201 FAMILY REGISTER 14-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 3 OC1TRIS: OC1 Output Tri-State Select bit 1 = OC1 output will not be active on the pin ...
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... Block diagrams of the module in Standard and Enhanced Buffer modes are displayed in Figure 15-1 and Figure 15-2. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The devices of the PIC24F04KA201 family offer one SPI module on a device. In this section, the SPI module is referred Note SPI1, or separately as SPI1. Special Function Registers (SFRs) will follow a similar notation ...
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... PIC24F04KA201 FAMILY FIGURE 15-1: SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 SS1/FSYNC1 Sync Control Control Clock SDO1 bit 0 SDI1 SPI1SR Transfer SPI1BUF Read SPI1BUF DS39937B-page 118 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPI1BUF 16 Internal Data Bus ...
Page 121
... SDI1 SPI1SR Transfer 8-Level FIFO Receive Buffer SPI1BUF Read SPI1BUF © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPI1BUF register using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register ...
Page 122
... PIC24F04KA201 FAMILY REGISTER 15-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 R-0,HSC R/C-0, HS R/W-0, HSC SRMPT SPIROV SRXMPT bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPI1 Enable bit ...
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... Automatically cleared in hardware when core reads SPI1BUF location, reading SPI1RXB. In Enhanced Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 121 ...
Page 124
... PIC24F04KA201 FAMILY REGISTER 15-2: SPI1CON1: SPI1 CONTROL REGISTER 1 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCK1 pin bit (SPI Master modes only) ...
Page 125
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — ...
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... PIC24F04KA201 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based OSC TABLE 15-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Based /2, Doze mode and PLL are disabled. Note 1: CY OSC SCK1 frequencies indicated in kHz. ...
Page 127
... Pin assignment is controlled by the I2C1SEL Configuration bit. Programming this bit (= 0) multiplexes the module to the SCL1 and SDA1 pins. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 16.2 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
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... PIC24F04KA201 FAMILY 2 FIGURE 16-1: I C™ BLOCK DIAGRAM Shift SCL1 Clock SDA1 Shift Clock BRG Down Counter DS39937B-page 126 I2C1RCV I2C1RSR LSB Address Match Match Detect I2C1ADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
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... Address will be Acknowledged only if GCEN = 1. 2: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 3: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 16.4 Slave Address Masking The I2C1MSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 130
... PIC24F04KA201 FAMILY REGISTER 16-1: I2C1CON: I2C1 CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit Hardware Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2C1 Enable bit 1 = Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins 0 = Disables the I2C1 module ...
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... Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating Initiates Start condition on SDA1 and SCL1 pins; hardware clear at end of master Start sequence 0 = Start condition not in progress © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 2 C master; applicable during master receive master ...
Page 132
... PIC24F04KA201 FAMILY REGISTER 16-2: I2C1STAT: I2C1 STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC IWCOL I2COV D/A bit Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
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... TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2C1TRN is full 0 = Transmit complete, I2C1TRN is empty Hardware set when software writes to I2C1TRN; hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 2 C slave device address byte. Preliminary DS39937B-page 131 ...
Page 134
... PIC24F04KA201 FAMILY REGISTER 16-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 135
... IrDA Hardware Flow Control UART1 Receiver UART1 Transmitter © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY • Fully Integrated Baud Rate Generator (IBRG) with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer • ...
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... PIC24F04KA201 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The U1BRG register controls the period of a free-running, 16-bit timer. Equation 17-1 provides the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: ...
Page 137
... FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 17.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Section 17.2 “Transmitting in 8-Bit Data Mode”). ...
Page 138
... PIC24F04KA201 FAMILY REGISTER 17-1: U1MODE: UART1 MODE REGISTER R/W-0 U-0 R/W-0 UARTEN — USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UART1 Enable bit 1 = UART1 is enabled; all UART1 pins are controlled by UART1 as defined by UEN<1:0> ...
Page 139
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is only available for the 16x BRG mode (BRGH = 0). Note 1: Bit availability depends on pin availability. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 137 ...
Page 140
... PIC24F04KA201 FAMILY REGISTER 17-2: U1STA: UART1 STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit Clearable bit Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL< ...
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... Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 139 ...
Page 142
... PIC24F04KA201 FAMILY REGISTER 17-3: U1TXREG: UART1 TRANSMIT REGISTER U-x U-x U-x — — — bit 15 W-x W-x W-x UTX7 UTX6 UTX5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode) bit 7-0 UTX< ...
Page 143
... V DD HLVDIN HLVDEN © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. ...
Page 144
... PIC24F04KA201 FAMILY REGISTER 18-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 HLVDEN — HLSIDL bit 15 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit ...
Page 145
... Selectable Buffer Fill modes • Four result alignment options • Operation during CPU Sleep and Idle modes On all PIC24F04KA201 family devices, the 10-bit A/D Converter has nine analog input pins, designated AN0 through AN5 and AN10 through AN12. In addition, there are two analog input pins for external voltage ...
Page 146
... PIC24F04KA201 FAMILY FIGURE 19-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM REF V - REF V INH AN0 AN1 AN2 AN1 AN3 V INL AN4 AN5 AN10 AN11 AN12 AN1 DS39937B-page 144 V INH S/H DAC V INL 10-Bit SAR Data Formatting ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS ...
Page 147
... A/D conversion is not done Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the Note 1: conversion values from the buffer before disabling the module. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — ...
Page 148
... PIC24F04KA201 FAMILY REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 bit 15 R-0, HSC U-0 R/W-0 BUFS — SMPI3 bit Unimplemented bit, read as ‘0’ Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG< ...
Page 149
... Unimplemented: Read as ‘0’ bit 5-0 ADCS<5:0>: A/D Conversion Clock Select bits 111111 = 32 • · · · 000001 = T CY 000000 = © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘0’ ...
Page 150
... PIC24F04KA201 FAMILY - REGISTER 19-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — bit 15 R/W-0 U-0 U-0 CH0NA — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit ...
Page 151
... Unimplemented: Read as ‘0’ bit 5-0 CSSL<5:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 PCFG10 ...
Page 152
... PIC24F04KA201 FAMILY EQUATION 19-1: A/D CONVERSION CLOCK PERIOD Based Note 1: CY FIGURE 19-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL ANx PIN 6-11 pF (Typical) Legend value depends on device package and is not tested. Effect of C Note: PIN DS39937B-page 150 ( ADCS = – • (ADCS + 1) ...
Page 153
... Voltage Level © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 151 ...
Page 154
... PIC24F04KA201 FAMILY NOTES: DS39937B-page 152 Preliminary © 2009 Microchip Technology Inc. ...
Page 155
... INA X CV REF © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module is displayed in Figure 20-1 ...
Page 156
... PIC24F04KA201 FAMILY FIGURE 20-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0 , CREF = x , CCH<1:0> Comparator CxINB > CxINA Compare CON = 1 , CREF = 0 , CCH<1:0> INB INA X Comparator CxINB > CV Compare REF CON = 1 , CREF = 1 , CCH<1:0> INB REF DS39937B-page 154 COE Off (Read as ‘0’) CxOUT Comparator V > CxINA Compare ...
Page 157
... Non-inverting input connects to CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects Inverting input of comparator connects to CxINB pin © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 CLPWR — — R/W-0 ...
Page 158
... PIC24F04KA201 FAMILY REGISTER 20-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 CMIDL — — bit 15 U-0 U-0 U-0 — — — bit 7 HSC = Hardware Settable/Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = When device enters Idle mode, the module does not generate interrupts ...
Page 159
... DD CVRSS = 0 CVREN CVRR V - REF © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 21.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 21-1). The comparator voltage reference provides two ranges of comprehensive output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON< ...
Page 160
... PIC24F04KA201 FAMILY REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
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... FIGURE 22-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT C APP © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 22.1 Measuring Capacitance The CTMU generating an output pulse with a width equal to the time between edge events on two separate input channels ...
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... PIC24F04KA201 FAMILY 22.2 Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s internal capacitor (C ) and a precision resistor for current calibration. AD Figure 22-2 displays the external connections used for time measurements, and how the CTMU and A/D modules are related in this application ...
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... CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 TGEN EDGEN EDGSEQEN R/W-0 R/W-0 ...
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... PIC24F04KA201 FAMILY REGISTER 22-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit ...
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... Section 36. “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725) • Section 33. “Programming and Diagnostics” (DS39716) PIC24F04KA201 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • Flexible Configuration • ...
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... PIC24F04KA201 FAMILY REGISTER 23-2: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER R/P-1 U-0 U-0 IESO — — bit 7 Legend Readable bit P = Programmable bit -n = Value at POR ‘1’ = Bit is set bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) ...
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... POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled Oscillator mode selected Oscillator mode selected 00 = External Clock mode selected © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/P-1 R/P-1 R/P Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/P-1 ...
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... PIC24F04KA201 FAMILY REGISTER 23-4: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 U-0 FWDTEN WINDIS — bit 7 Legend Readable bit P = Programmable bit -n = Value at POR ‘1’ = Bit is set bit 7 FWDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) ...
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... Unimplemented: Read as ‘0’ bit 1-0 FICD<1:0:> ICD Pin Select bits 10 = PGC2/PGD2 are used for programming the device 01 = PGC3/PGD3 are used for programming the device 00 Reserved; do not use © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 R/P-1 (2) — PWRTEN U = Unimplemented bit, read as ‘0’ ...
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... PIC24F04KA201 FAMILY REGISTER 23-7: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 U-0 DSWDTEN DSLPBOR — bit 7 Legend Readable bit P = Programmable bit -n = Value at POR ‘1’ = Bit is set bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled 0 = DSWDT disabled bit 6 DSLPBOR: Deep Sleep/Low-Power BOR Enable bit (does not affect operation in non Deep Sleep modes) ...
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... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘0’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 00001011 = PIC24F04KA201 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00000000 = PIC24F04KA201 00000010 = PIC24F04KA200 REGISTER 23-9: DEVREV: DEVICE REVISION REGISTER ...
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... PIC24F04KA201 FAMILY 23.2 Watchdog Timer (WDT) For the PIC24F04KA201 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...
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... Deep Sleep Watchdog Timer (DSWDT) In PIC24F04KA201 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWCKSEL (FDS<4>). The DSWDT can be configured to generate a time-out at 2 ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 172 Preliminary © 2009 Microchip Technology Inc. ...
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... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 24.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... PIC24F04KA201 FAMILY 24.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
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... Microchip Technology Inc. PIC24F04KA201 FAMILY 24.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, connecting to the host PC via an RS-232 or high-speed USB interface ...
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... PIC24F04KA201 FAMILY 24.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins ...
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... The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘ ...
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... PIC24F04KA201 FAMILY TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select ...
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... BSW BSW.C Ws,Wb BSW.Z Ws,Wb BTG BTG f,#bit4 BTG Ws,#bit4 BTSC BTSC f,#bit4 BTSC Ws,#bit4 © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Description WREG WREG = f + WREG Wd = lit10 + lit5 WREG + (C) WREG = f + WREG + ( lit10 + lit5 + ( .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND .AND ...
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... PIC24F04KA201 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Assembly Syntax Mnemonic BTSS BTSS f,#bit4 BTSS Ws,#bit4 BTST BTST f,#bit4 BTST.C Ws,#bit4 BTST.Z Ws,#bit4 BTST.C Ws,Wb BTST.Z Ws,Wb BTSTS BTSTS f,#bit4 BTSTS.C Ws,#bit4 BTSTS.Z Ws,#bit4 CALL CALL lit23 CALL Wn CLR CLR ...
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... POP f POP Wdo POP.D Wnd POP.S PUSH PUSH f PUSH Wso PUSH.D Wns PUSH.S © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Description Go to Address Go to Indirect WREG = WREG = .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR .IOR .IOR. lit5 Link Frame Pointer f = Logical Right Shift f ...
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... PIC24F04KA201 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Assembly Syntax Mnemonic PWRSAV PWRSAV #lit1 RCALL RCALL Expr RCALL Wn REPEAT REPEAT #lit14 REPEAT Wn RESET RESET RETFIE RETFIE RETLW RETLW #lit10,Wn RETURN RETURN RLC RLC f RLC f,WREG RLC Ws,Wd RLNC RLNC f RLNC ...
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... XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws Preliminary ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 184 Preliminary © 2009 Microchip Technology Inc. ...
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... ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F04KA201 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F04KA201 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. († ...
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... PIC24F04KA201 FAMILY 26.1 DC Characteristics FIGURE 26-1: PIC24F04KA201 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.00V 1.80V For frequencies between 8 MHz and 32 MHz, F Note: TABLE 26-1: THERMAL OPERATING CONDITIONS Rating Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: – ...
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... Operating temperature -40°C ≤ T ≤ +85°C for industrial A Param Symbol Characteristic No. DC18 V HLVD Voltage on V HLVD Transition © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature (1) Min Typ Max Units 1.8 — 3.6 V 1.5 — ...
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... PIC24F04KA201 FAMILY TABLE 26-5: BOR TRIP POINTS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ≤ +85°C for industrial Operating temperature A Param Sym Characteristic No. DC19 BOR Voltage on V Transition BOR = 00 1.55 DD TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS (1) Parameter No. Typical Max ...
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... MCLR – • WDT FSCM disabled • SRAM, program and data memory active • All PMD bits set except for modules being measured © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY DD Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature A Units -40° ...
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... PIC24F04KA201 FAMILY TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS (1) Param No. Typical Max Idle Current (I ): Core Off, Clock on Base Current, PMD Bits are Set IDLE DC42 200 DC42a 200 94 DC42b 200 DC42c 200 DC42d 395 DC42e 395 160 DC42f 395 DC42g 395 DC43 6 ...
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... The Δ current is the additional current consumed when the module is enabled. This current should be added to 3: the base I current. PD Current applies to Sleep only. 4: Current applies to Deep Sleep only. 5: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A Units (2) -40°C +25°C μ ...
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... PIC24F04KA201 FAMILY TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. Power-Down Current (I ): PMD Bits are Set, PMSLP Bit is ‘0’ PD DC62 0.650 DC62a 0.650 0.450 DC62b 0.650 DC62c 0.650 DC62d 0.980 DC62e 0.980 0.730 DC62f 0.980 DC62g 0.980 DC64 7 ...
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... The Δ current is the additional current consumed when the module is enabled. This current should be added to 3: the base I current. PD Current applies to Sleep only. 4: Current applies to Deep Sleep only. 5: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A Units (2) -40°C +25°C μ ...
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... PIC24F04KA201 FAMILY TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Sym Characteristic No. ( Input Low Voltage DI10 I/O Pins MCLR DI15 DI16 OSCI (XT mode) DI17 OSCI (HS mode) 2 DI18 I/O Pins with I C™ Buffer DI19 I/O Pins with SMBus Buffer ( Input High Voltage ...
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... DDP Programming Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Note 1: Self-write and block erase. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A (1) ...
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... PIC24F04KA201 FAMILY TABLE 26-12: COMPARATOR DC SPECIFICATIONS Operating Conditions: 2.0V < V < 3.6V, -40°C < Param Symbol Characteristic No. D300 V Input Offset Voltage* IOFF D301 V Input Common Mode Voltage* ICM D302 CMRR Common Mode Rejection Ratio* * Parameters are characterized but not tested. TABLE 26-13: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS Operating Conditions: 2.0V < ...
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... AC Characteristics and Timing Parameters The information contained in this section defines the PIC24F04KA201 family AC characteristics and timing parameters. TABLE 26-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature AC CHARACTERISTICS Operating voltage V FIGURE 26-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – ...
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... PIC24F04KA201 FAMILY FIGURE 26-3: EXTERNAL CLOCK TIMING OSCI OS25 CLKO TABLE 26-19: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym Characteristic No. OS10 F External CLKI Frequency OSC (External clocks allowed only in EC mode) Oscillator Frequency OS20 1/F OSC OSC OSC OS25 T Instruction Cycle Time ...