PIC16F628A-I/SO Microchip Technology, PIC16F628A-I/SO Datasheet
PIC16F628A-I/SO
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PIC16F628A-I/SO Summary of contents
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... Microcontrollers with nanoWatt Technology 2004 Microchip Technology Inc. PIC16F627A/628A/648A Flash-Based 8-Bit CMOS Preliminary Data Sheet DS40044B ...
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... ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. ...
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... Flash endurance - 1,000,000 write EEPROM endurance - 100 year data retention Program Memory Device Flash (words) PIC16F627A 1024 PIC16F628A 2048 PIC16F648A 4096 2004 Microchip Technology Inc. PIC16F627A/628A/648A Low Power Features: • Standby Current: - 100 nA @ 2.0V, typical • Operating Current kHz, 2 ...
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... RA2/AN2/V REF RA3/AN3/CMP1 2 RA4/TOCKI/CMP2 3 4 RA5/MCLR RB0/INT 6 RB1/RX/ RB2/TX/CK RB3/CCP1 9 SSOP PIC16F627A/628A/648A DS40044B-page 2 18 RA1/AN1 17 RA0/AN0 16 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RB7/T1OSI/PGD 13 12 RB6/T1OSO/T1CKI/PGC RB5 11 10 RB4/PGM 28-Pin QFN RA5/MCLR PIC16F627A/628A NC 4 PIC16F648A RB0/INT 7 Preliminary 21 RA7/OSC1/CLKIN 20 RA6/OSC2/CLKOUT RB7/T1OSI/PGD 15 RB6/T1OSO/T1CKI/PGC 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Preliminary DS40044B-page 3 ...
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... PIC16F627A/628A/648A NOTES: DS40044B-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... Development Support The PIC16F627A/628A/648A family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low cost in-circuit debugger, a low cost development programmer and a full-featured programmer. A Third Party “C” compiler support tool is also available. PIC16F628A PIC16F648A PIC16LF627A 2048 4096 1024 ...
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... PIC16F627A/628A/648A NOTES: DS40044B-page 6 Preliminary 2004 Microchip Technology Inc. ...
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... The devices are standard Flash devices but with all program locations and configuration options already programmed by the factory. Certain code and prototype verification procedures production shipments are available. Please contact your Microchip Technology sales office for more details. 2.3 Serialized Quick-Turnaround- SM Production (SQTP ) Devices ...
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... PIC16F627A/628A/648A NOTES: DS40044B-page 8 Preliminary 2004 Microchip Technology Inc. ...
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... Table 3-1 lists device memory sizes (Flash, Data and EEPROM). TABLE 3-1: DEVICE MEMORY LIST Memory Device Flash RAM Program Data PIC16F627A 1024 x 14 224 x 8 PIC16F628A 2048 x 14 224 x 8 PIC16F648A 4096 x 14 256 x 8 PIC16LF627A 1024 x 14 224 x 8 PIC16LF628A 2048 x 14 224 x 8 PIC16LF648A ...
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... Timer Oscillator ALU Power-on 8 Reset Watchdog W reg Timer Brown-out Detect Low-Voltage Timer1 Timer2 USART Data EEPROM Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/V REF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/V PP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN PORTB RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 RB4/PGM RB5 RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD 2004 Microchip Technology Inc. ...
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... RB1 RX DT RB2/TX/CK RB2 TX CK RB3/CCP1 RB3 CCP1 Legend Output — = Not used TTL = TTL Input 2004 Microchip Technology Inc. PIC16F627A/628A/648A Input Type Output Type ST CMOS Bidirectional I/O port AN — Analog comparator input ST CMOS Bidirectional I/O port AN — Analog comparator input ...
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... CMOS ICSP Data I/O Power — Ground reference for logic and I/O pins Power — Positive supply for logic and I/O pins CMOS = CMOS Output I = Input OD = Open Drain Output Preliminary Description P = Power ST = Schmitt Trigger Input AN = Analog 2004 Microchip Technology Inc. ...
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... PORTA, 3 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4) ...
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... PIC16F627A/628A/648A NOTES: DS40044B-page 14 Preliminary 2004 Microchip Technology Inc. ...
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... Only the first (0000h - 03FFh) for the PIC16F627A (0000h - 07FFh) for the PIC16F628A and (0000h - 0FFFh) for the PIC16F648A are physically implemented. Accessing a location above these boundaries will cause a wrap- around within the first space (PIC16F627A space (PIC16F628A space (PIC16F648A) ...
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... PIC16F627A/628A/648A FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A (1) Indirect addr. Indirect addr. 00h 01h TMR0 02h PCL STATUS 03h FSR 04h 05h PORTA PORTB 06h 07h 08h 09h PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh TMR1L 0Eh TMR1H 0Fh ...
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... CMCON 20h General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2004 Microchip Technology Inc. PIC16F627A/628A/648A (1) (1) Indirect addr. 80h TMR0 OPTION 81h PCL PCL 82h STATUS STATUS ...
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... T2CKPS1 T2CKPS0 -000 0000 52 — — — — 55 xxxx xxxx 55 xxxx xxxx CCP1M1 CCP1M0 55 --00 0000 OERR RX9D 69 0000 000x 76 0000 0000 79 0000 0000 — — — — — — — — CM1 CM0 61 0000 0000 2004 Microchip Technology Inc. ...
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... VREN VROE Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unim- plemented Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 ...
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... Microchip Technology Inc. ...
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... Unimplemented Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS ...
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... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-x R/W-x R/W bit Bit is unknown 2004 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC16F627A/628A/648A Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 "Switching Prescaler Assignment". R/W-1 R/W-1 R/W-1 T0CS ...
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... GIE (INTCON<7>). and R/W-0 R/W-0 R/W-0 T0IE INTE RBIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-x T0IF INTF RBIF bit Bit is unknown 2004 Microchip Technology Inc. ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 U-0 RCIE TXIE — CCP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... R-0 R-0 U-0 R/W-0 RCIF TXIF — CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2004 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC16F627A/628A/648A Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR is cleared, occurred. The BOR Status bit is a “ ...
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... Example 4-1. EXAMPLE 4-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO RETLW or a Preliminary Indirect Addressing 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue 2004 Microchip Technology Inc. ...
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... RP1 RP0 6 bank select location select 00h RAM File Registers 7Fh Bank 0 Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Status Register 0 IRP bank select 180h Bank 1 Bank 2 ...
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... PIC16F627A/628A/648A NOTES: DS40044B-page 30 Preliminary 2004 Microchip Technology Inc. ...
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... The user must make sure to keep the pins configured as inputs when using them as comparator inputs. 2004 Microchip Technology Inc. PIC16F627A/628A/648A The RA2 pin will also function as the output for the voltage reference. When in this mode, the V very high-impedance output. The user must configure TRISA< ...
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... D Q Comparator Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA To Comparator DS40044B-page RA2 Pin Comparator Mode = 110 (CMCON Reg Preliminary V DD RA3 Pin Analog V Input Mode SS (CMCON Reg.) Schmitt Trigger Input Buffer D EN 2004 Microchip Technology Inc. ...
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... Bit) MCLRE MCLR circuit MCLR Filter Schmitt Trigger Program Input Buffer mode HV Detect Data Bus RD V TRISA PORTA 2004 Microchip Technology Inc. PIC16F627A/628A/648A Comparator Mode = 110 (CMCON Reg FIGURE 5-6: PIN PP From OSC1 CLKOUT(F OSC D WR PORTA OSC Data Latch ...
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... BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To Clock Circuits Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA ( 100, 101 OSC RD PORTA Note 1: INTOSC with CLKOUT, and INTOSC with I/O. DS40044B-page Schmitt Trigger Input Buffer EN Preliminary V DD RA7/OSC1/CLKIN Pin V SS 2004 Microchip Technology Inc. ...
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... MCLR V PP RA6/OSC2/CLKOUT RA6 OSC2 CLKOUT RA7/OSC1/CLKIN RA7 OSC1 XTAL CLKIN Legend Output — = Not used TTL = TTL Input 2004 Microchip Technology Inc. PIC16F627A/628A/648A Output Type Type ST CMOS Bidirectional I/O port AN — Analog comparator input ST CMOS Bidirectional I/O port AN — ...
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... Polling of PORTB is not recommended while using the interrupt-on-change feature. Preliminary (1) Value on Value on Bit 0 All Other POR Resets RA0 xxxx 0000 qqqu 0000 TRISA0 1111 1111 1111 1111 CM0 0000 0000 0000 0000 VR0 000- 0000 000- 0000 2004 Microchip Technology Inc. ...
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... WR PORTB CK Q Data Latch TRISB CK Q TRIS Latch TTL RD TRISB Input Buffer PORTB INT Schmitt Trigger 2004 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 5- RBPU Weak Pull-up P SPEN V DD USART Data Output Data Bus RB0/INT WR PORTB TRISB (1) Peripheral OE RD TRISB RD PORTB USART Receive Input ...
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... Peripheral OE TTL Input RD TRISB Buffer RD PORTB CCP In Note 1: Peripheral OE (output enable) is only active if peripheral select is active. Preliminary BLOCK DIAGRAM OF RB3/CCP1 PIN V DD Weak Pull- RB3 CCP1 CK Q Data Latch TRIS Latch TTL Input Buffer Schmitt Trigger 2004 Microchip Technology Inc. ...
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... D WR TRISB CK TRIS Latch RD TRISB LVP (Configuration Bit) RD PORTB PGM input Set RBIF From other RB<7:4> pins Note: The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Schmitt Trigger Q Q Preliminary weak pull-up ...
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... PIC16F627A/628A/648A FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS40044B-page 40 TTL input buffer Preliminary 2004 Microchip Technology Inc weak P pull-up RB5 pin ...
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... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN RBPU Data Bus WR PORTB WR TRISB TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial programming clock Set RBIF 2004 Microchip Technology Inc. PIC16F627A/628A/648A Data Latch Schmitt Trigger From other RB<7:4> pins Preliminary V DD ...
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... Data Bus WR PORTB WR TRISB RD TRISB T10SCEN RD PORTB Serial programming input Set RBIF DS40044B-page Data Latch TRIS Latch Q Q From other RB<7:4> pins EN Preliminary V DD weak pull-up P TMR1 oscillator V DD RB7/T1OSI pin V SS TTL input buffer Schmitt Trigger 2004 Microchip Technology Inc. ...
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... OPTION RBPU INTEDG Legend unchanged unknown Note 1: Shaded bits are not used by PORTB. 2: LVP Configuration Bit sets RB4 functionality. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Output Type TTL CMOS Bidirectional I/O port. Can be software programmed for internal weak pull-up. ...
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... T = instruction cycle and T = propagation delay of Q1 cycle to output valid Preliminary READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT PORTB<3:0> Outputs PORT latchPORT Pins ---------- ---------- ; ;01pp pppp 11pp pppp ; ;10pp pppp 11pp pppp ;10pp pppp 10pp pppp NOP Execute NOP 2004 Microchip Technology Inc. ...
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... Timer0 module interrupt service routine before re- enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements ...
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... CYCLES 0 T0CS PSA WDT POSTSCALER/ TMR0 PRESCALER 8 8-TO-1MUX PS0 - PS2 1 WDT TIME OUT 0 PSA Preliminary the TMR0 register (e.g., CLRF 1, x....etc.) will clear the BSF 1, DATA BUS 8 TMR0 REG SET FLAG BIT T0IF ON OVERFLOW 2004 Microchip Technology Inc. ...
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... Unimplemented locations, read as ‘0’ unchanged unknown Note 1: Shaded bits are not used by Timer0 module. 2: Option is referred by OPTION_REG in MPLAB 2004 Microchip Technology Inc. PIC16F627A/628A/648A To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled ...
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... R/W-0 R/W-0 R/W-0 — T1CKPS1 T1CKPS0 T1OSCEN (1) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (CCP) Module"). R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown 2004 Microchip Technology Inc. ...
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... TMR1 TMR1H T1OSC RB6/T1OSO/T1CKI RB7/T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 7.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE When an external clock input is used for Timer1 in synchronized Counter mode, it must meet certain requirements ...
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... MOVF TMR1H, W MOVWF TMPH MOVF TMR1L, W MOVWF TMPL ; Re-enable the Interrupts (if required) CONTINUE Preliminary 2004 Microchip Technology Inc. ;Read high byte ; ;Read low byte ; ;Read high byte ;Sub 1st read with ;2nd read ;Is result = 0 ;Good 16-bit read ;Read high byte ...
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... T1CON — — T1CKPS1 Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 7.5 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will Reset Timer1 ...
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... Synchronous Serial Port module which optionally uses it to generate shift clock. FIGURE 8-1: Sets flag TMR2 bit TMR2IF output Reset Postscaler 1:1 to 1:16 4 TOUTPS<3:0> Preliminary TIMER2 BLOCK DIAGRAM Prescaler TMR2 reg F /4 OSC 1:1, 1:4, 1:16 2 Comparator EQ T2CKPS<1:0> PR2 reg 2004 Microchip Technology Inc. ...
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... T2CON — 92h PR2 Timer2 Period Register Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module. 2004 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 R/W-0 TOUTPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
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... PIC16F627A/628A/648A NOTES: DS40044B-page 54 Preliminary 2004 Microchip Technology Inc. ...
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... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 11xx = PWM mode Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 9-1: CCP Mode Capture Compare PWM ...
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... CCP module off ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value COMPARE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Output Comparator Logic match TMR1H TMR1L CCP1CON<3:0> Mode Select 2004 Microchip Technology Inc. ...
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... CCP1X Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 9.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled) ...
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... PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Preliminary PWM OUTPUT Period TMR2 = PR2 TMR2 = Duty Cycle PR2 + 1 4 Tosc TMR2 prescale value 2004 Microchip Technology Inc. ...
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... CCPR1H 17h CCP1CON — — Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Maximum PWM resolution (bits) for a given PWM frequency: PWM Resolution Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared ...
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... PIC16F627A/628A/648A NOTES: DS40044B-page 60 Preliminary 2004 Microchip Technology Inc. ...
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... CM2:CM0: Comparator Mode Figure 10-1 shows the Comparator modes and CM2:CM0 bit settings Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC16F627A/628A/648A The CMCON register, shown in Register 10-1, controls the comparator input and output multiplexers. A block two analog diagram of the comparator is shown in Figure 10-1 ...
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... D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch. Preliminary Off (Read as '0 Off (Read as '0 CIS = CIS = 1 C1V OUT CIS = 0 IN CIS = 1 C2V OUT From V REF Module C1V OUT C2V OUT CIS = CIS = 1 C1V OUT C2V OUT 2004 Microchip Technology Inc. ...
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... Comparator Reference An external or internal reference signal may be used depending on the comparator Operating mode. The analog signal that is present compared to the IN signal and the digital output of the comparator IN is adjusted accordingly (Figure 10-2). 2004 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 10-2: Vin+ Vin ...
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... FIGURE 10-3: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM CnI NV To RA3 or RA4/T0CK1 pin To Data Bus CMCON<7:6> RD CMCON Set CMIF bit From other Comparator DS40044B-page Reset Preliminary 2004 Microchip Technology Inc. CnV OUT Q3 Q1 ...
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... Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 10.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled ...
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... CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 Preliminary R IC Value on Value on Bit 0 All Other POR Resets CM0 0000 0000 0000 0000 RBIF 0000 000x 0000 000u 2004 Microchip Technology Inc. ...
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... R = Readable bit -n = Value at POR FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM REN 8R V REF Note defined in Table 17-3. 2004 Microchip Technology Inc. PIC16F627A/628A/648A The equations used to calculate the output of the Voltage Reference are as follows REF The setting time of the Voltage Reference must be considered when changing the V (Table 17-3) ...
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... The V RR REF Reference Module operates bit, ROE enabled will also increase REF V Output REF Value On Value On Bit 0 All Other POR Resets VR0 000- 0000 000- 0000 CM0 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111 2004 Microchip Technology Inc. ...
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... TX9D: 9th bit of transmit data. Can be parity bit. Note: SREN/CREN overrides TXEN in SYNC mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC16F627A/628A/648A The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous - Master (half-duplex) • Synchronous - Slave (half-duplex) Bit SPEN (RCSTA< ...
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... R = Readable bit -n = Value at POR DS40044B-page 70 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown 2004 Microchip Technology Inc. ...
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... RCSTA SPEN RX9 99h SPBRG Legend unknown unimplemented read as ‘0’. Shaded cells are not used by the BRG. 2004 Microchip Technology Inc. PIC16F627A/628A/648A EXAMPLE 12-1: Desired Baud Rate , the nearest Calculated Baud Rate (Calculated Baud Rate - Desired Baud Rate) --------------------------------------------------------------------------------------------------------- - ...
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... SPBRG value KBAUD ERROR (decimal) 0.303 +1.14% 26 1.170 -2.48 — — NA — — NA — — NA — — NA — — NA — — — — 8.192 — 0 0.032 — 255 2004 Microchip Technology Inc. ...
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... NA — — 300 NA — 500 NA — HIGH 55.93 — LOW 0.2185 — 2004 Microchip Technology Inc. PIC16F627A/628A/648A 16 MHz SPBRG value value KBAUD ERROR (decimal) — NA — — 255 1.202 +0.16% 207 129 2.404 +0.16% 103 32 9 ...
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... NA — — 625 — — 4 MHz SPBRG value KBAUD ERROR (decimal) 9615.385 0.160% 25 19230.77 0.160% 12 35714.29 -6.994% 6 62500 8.507% 3 125000 8.507% 1 250000 0.000 — — NA — — 32.768 kHz SPBRG value KBAUD ERROR (decimal 2004 Microchip Technology Inc. ...
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... RX pin Baud CLK x4 CLK Q2, Q4 CLK FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1 RX pin Baud CLK First falling edge after RX pin goes low x4 CLK Q2, Q4 CLK 2004 Microchip Technology Inc. PIC16F627A/628A/648A Start bit Baud CLK for all but Start bit ...
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... This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit maybe loaded in the TSR register. bit TXIE Preliminary bit 2004 Microchip Technology Inc. ...
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... RB2/TX/CK (pin) Start Bit TXIF bit (Transmit buffer reg. empty flag) WORD 1 TRMT bit Transmit Shift Reg (Transmit shift reg. empty flag) 2004 Microchip Technology Inc. PIC16F627A/628A/648A Data Bus TXREG register 8 MSb LSb (8) 0 ² ² ² TSR register ...
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... Transmit Shift Reg. Value on Value on Bit 0 all other POR Resets TMR1IF 0000 -000 0000 -000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TMR1IE 0000 -000 0000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
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... RX9 ADEN RX9 ADEN RSR<8> 2004 Microchip Technology Inc. PIC16F627A/628A/648A double buffered register, (i.e two deep FIFO possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full then overrun error bit OERR (RCSTA< ...
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... STOP BIT8 STOP BIT BIT0 BIT8 BIT BIT WORD 1 BIT8 = 0, DATA BYTE RCREG START STOP BIT8 STOP BIT BIT0 BIT8 BIT BIT WORD 1 BIT8 = 0, DATA BYTE RCREG Preliminary WORD 1 RCREG ‘1’ ‘1’ WORD 2 RCREG 2004 Microchip Technology Inc. ...
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... EEIE CMIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF — ...
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... BRGH TRMT Baud Rate Generator Register Preliminary enabled by setting bit CREN Value on Value on Bit 0 all other POR Resets RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
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... TSR register is empty transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Clearing enable bit TXEN, during a transmission, will cause the transmission to be aborted and will Reset the transmitter ...
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... Preliminary Value on Value on all Bit 0 POR other Resets 0000 -000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 BIT 1 BIT 7 ‘1’ BIT6 BIT7 2004 Microchip Technology Inc. ...
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... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception. 2004 Microchip Technology Inc. PIC16F627A/628A/648A with a new value, therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information ...
Page 88
... If 9-bit transmission is desired, then set bit TX9. 6. Enable the transmission by setting enable bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 8. Start transmission by loading data to the TXREG register. Preliminary Q1Q2Q3Q4 BIT6 BIT7 ‘0’ 2004 Microchip Technology Inc. ...
Page 89
... TXEN SYNC 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 2. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC ...
Page 90
... PIC16F627A/628A/648A NOTES: DS40044B-page 88 Preliminary 2004 Microchip Technology Inc. ...
Page 91
... EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC16F627A/628A/648A The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...
Page 92
... Data EEPROM write sequence. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 93
... After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. 2004 Microchip Technology Inc. PIC16F627A/628A/648A At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set ...
Page 94
... EE writes ;enable interrupts (optional) Bit 5 Bit 4 Bit 3 Bit 2 — — WRERR WREN Preliminary Value on Value on all Bit 1 Bit 0 Power-on other Reset Resets xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu WR RD ---- x000 ---- q000 ---- ---- ---- ---- 2004 Microchip Technology Inc. ...
Page 95
... The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 14.1 Configuration Bits The configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘ ...
Page 96
... CP: Flash Program Memory Code Protection bit (PIC16F648A Code protection off 0 = 0000h to 0FFFh code protected (PIC16F628A Code protection off 0 = 0000h to 07FFh code protected (PIC16F627A Code protection off 0 = 0000h to 03FFh code protected bit 12-9: Unimplemented: Read as ‘0’ ...
Page 97
... C2 PIC16F627A/628A/648A Note 1: A series resistor may be required for AT strip cut crystals. 2: See Table 14-1 and Table 14-2 for recommended values of C1 and C2. 2004 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 14-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Mode Freq XT 455 kHz 2.0 MHz 4 ...
Page 98
... The oscillator frequency, divided by 4 can be used for test purposes or to synchronize other logic. Preliminary EXTERNAL CLOCK INPUT OPERATION (EC, HS OSC CONFIGURATION) RA7/OSC1/CLKIN PIC16F627A/628A/648A RA6/OSC2/CLKOUT ) values EXT RC OSCILLATOR MODE PIC16F627A/628A/648A Internal Clock 2004 Microchip Technology Inc. ...
Page 99
... OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter OSC Note 1: This is a separate oscillator from the INTOSC/RC oscillator. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 14.3 Reset The PIC16F627A/628A/648A differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep ...
Page 100
... PWRTE bit is programmed to ‘0’. Preliminary for longer than T , BOR BOR falls below V for DD BOR . V and T are defined in BOR BOR rises above DD while the Power-up Timer is BOR DD , the Power-Up Timer will execute a V BOR V BOR V BOR 2004 Microchip Technology Inc. ...
Page 101
... Legend unchanged unknown 2004 Microchip Technology Inc. PIC16F627A/628A/648A 14.4.6 POWER CONTROL (PCON) STATUS REGISTER The power control/Status Register, PCON (address 8Eh) has two bits. Bit 0 is BOR (Brown-out Reset). BOR is unknown on Power-on-Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0 ...
Page 102
... uuu0 0uuu 000h 000x xuuu ( uuu1 0uuu Preliminary Value on all Value on Bit 0 other POR Reset (1) Resets C 0001 1xxx 000q quuu BOR ---- 1-0x ---- u-uq PCON Register ---- 1-0x ---- 1-uu ---- 1-uu ---- 1-uu ---- u-uu ---- 1-u0 ---- u-uu 2004 Microchip Technology Inc. ...
Page 103
... If Reset was due to brown-out, then bit All other Resets will cause bit Reset to ‘ 00 0000’ Brown-out Reset (BOR Peripherals generating interrupts for wake-up from Sleep will change the resulting bits in the associated registers. 2004 Microchip Technology Inc. PIC16F627A/628A/648A • MCLR Reset during normal • Wake-up from Sleep operation • ...
Page 104
... PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET DS40044B-page 102 Tpwrt Tost Tpwrt Tost Tpwrt Tost Preliminary 2004 Microchip Technology Inc. ): CASE DD ): CASE ...
Page 105
... MCLR 40k PIC16F627A/628A/648A Note 1: This circuit will activate Reset when V goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit. 2004 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 14-13 Note 1: This Brown-out Circuit is less expensive, albeit less accurate. Transistor Q1 turns off ...
Page 106
... GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again. T0IF T0IE INTF INTE RBIF RBIE PEIE GIE Preliminary of the status of their Wake-up (If in Sleep mode) Interrupt to CPU 2004 Microchip Technology Inc. ...
Page 107
... Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT is available in RC and INTOSC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 14.5.3 PORTB INTERRUPT An input change on PORTB < ...
Page 108
... Bit 0 other POR Reset (1) Resets RBIF 0000 000x 0000 000u 0000 -000 0000 -000 0000 -000 0000 -000 SLEEP instruction. During normal oper- bit WDTE as clear and instructions clear the WDT SLEEP = Min., Temperature = Max., max. 2004 Microchip Technology Inc. ...
Page 109
... PD bit in the Status Register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP was executed (driving high, low, or hi-impedance). 2004 Microchip Technology Inc. PIC16F627A/628A/648A 0 M WDT POSTSCALER/ U TMR0 PRESCALER ...
Page 110
... Only the Least Significant 4 bits of the user ID locations are used. Preliminary instruction is being executed, the instruction. If the GIE bit is SLEEP is not desirable, the SLEEP after the instruction. NOP SLEEP 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) 2004 Microchip Technology Inc. ...
Page 111
... Data I/O RB7/PGD Normal Connections 2004 Microchip Technology Inc. PIC16F627A/628A/648A 14.12 Low Voltage Programming The LVP bit of the configuration word, enables the low voltage programming. This mode allows the microcon- troller to be programmed via ICSP using only a 5V source. This mode removes the requirement placed on the MCLR pin ...
Page 112
... PIC16F627A/628A/648A NOTES: DS40044B-page 110 Preliminary 2004 Microchip Technology Inc. ...
Page 113
... Assigned to < > Register bit field In the set of italics User defined term (font is courier) 2004 Microchip Technology Inc. PIC16F627A/628A/648A The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 114
... Preliminary 2004 Microchip Technology Inc. Status Notes Affected LSb C,DC,Z 1,2 ffff Z 1,2 ffff Z 2 ffff Z 0011 Z 1,2 ffff Z 1,2 ffff 1,2,3 ffff ...
Page 115
... Words: 1 Cycles: 1 Example ADDWF REG1, 0 Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0xD9 REG1 = 0xC2 2004 Microchip Technology Inc. PIC16F627A/628A/648A ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: . Words: Cycles: Example ANDWF Syntax: f,d Operands: Operation: Status Affected: ...
Page 116
... NOP is executed instead, making this a two- . cycle instruction 1 1(2) HERE BTFSC REG1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address HERE After Instruction if REG<1> address TRUE if REG<1>= address FALSE 2004 Microchip Technology Inc. ...
Page 117
... BTFSS FALSE GOTO TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> address FALSE if FLAG<1> address TRUE 2004 Microchip Technology Inc. PIC16F627A/628A/648A CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: Words: Cycles: REG1 PROCESS_CODE Example CLRF ...
Page 118
... Z 00 0011 dfff ffff Decrement register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’ DECF CNT, 1 Before Instruction CNT = 0x01 After Instruction CNT = 0x00 2004 Microchip Technology Inc. ...
Page 119
... CONTINUE • • • Before Instruction PC = address After Instruction REG1 = REG1 - 1 if REG1 = address CONTINUE if REG1 address HERE+1 2004 Microchip Technology Inc. PIC16F627A/628A/648A GOTO Syntax: Operands: Operation: skip if result = Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example REG1, 1 LOOP ...
Page 120
... A NOP is executed instead making it a two-cycle instruction. 1 1(2) HERE INCFSZ REG1, 1 GOTO LOOP CONTINUE • • • Before Instruction PC = address HERE After Instruction REG1 = REG1 + 1 if CNT = address CONTINUE if REG1 address HERE +1 2004 Microchip Technology Inc. ...
Page 121
... Words: 1 Cycles: 1 Example IORWF REG1, 0 Before Instruction REG1 = 0x13 W = 0x91 After Instruction REG1 = 0x13 W = 0x93 2004 Microchip Technology Inc. PIC16F627A/628A/648A MOVLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example MOVF f,d Syntax: Operands: ...
Page 122
... GIE None 00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two- cycle instruction RETFIE After Interrupt PC = TOS GIE = 1 2004 Microchip Technology Inc. ...
Page 123
... POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS 2004 Microchip Technology Inc. PIC16F627A/628A/648A RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: ...
Page 124
... The W register is subtracted (2’s complement method) from the eight bit literal ‘k’. The result is placed in the W register SUBLW 0x02 Before Instruction After Instruction result is positive Before Instruction After Instruction result is zero Before Instruction After Instruction W = 0xFF result is negative 2004 Microchip Technology Inc. ...
Page 125
... REG1 = result is zero Example 3: Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative 2004 Microchip Technology Inc. PIC16F627A/628A/648A SWAPF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: ...
Page 126
... Exclusive OR the contents of the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’ XORWF REG1, 1 Before Instruction REG1 = 0xAF W = 0xB5 After Instruction REG1 = 0x1A W = 0xB5 2004 Microchip Technology Inc. ...
Page 127
... OQ - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2004 Microchip Technology Inc. PIC16F627A/628A/648A 16.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 128
... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary 2004 Microchip Technology Inc. economical software ...
Page 129
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 16.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 130
... H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a proto- typing area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. Preliminary 2004 Microchip Technology Inc. ...
Page 131
... PIC Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2004 Microchip Technology Inc. PIC16F627A/628A/648A 16.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB A microcontrollers ...
Page 132
... PIC16F627A/628A/648A NOTES: DS40044B-page 130 Preliminary 2004 Microchip Technology Inc. ...
Page 133
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 pulling this pin directly to V 2004 Microchip Technology Inc. PIC16F627A/628A/648A ............................................................................................-0.3 to +14V SS ....................................................................................-0. ...
Page 134
... The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-2: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40 C 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 2.0 0 Note: The shaded region indicates the permissible combinations of voltage and frequency. DS40044B-page 132 4 10 FREQUENCY (MHz FREQUENCY (MHz) Preliminary TA +125 + 2004 Microchip Technology Inc. ...
Page 135
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which V can be lowered in Sleep mode without losing RAM data. DD 2004 Microchip Technology Inc. PIC16F627A/628A/648A Standard Operating Conditions (unless otherwise stated) Operating temperature -40 C ...
Page 136
... Preliminary Conditions Note WDT, BOR, Comparators and REF T1OSC: disabled WDT Current BOR Current Comparator Current V Current REF T1O Current kHz OSC LP Oscillator Mode MHz OSC XT Oscillator Mode MHz OSC XT Oscillator Mode MHz OSC HS Oscillator Mode 2004 Microchip Technology Inc. ...
Page 137
... Note 1: The “ ” current is the additional current consumed when this peripheral is enabled. This current should be added to the base measurement. Max values should be used when calculating total current consumption 2004 Microchip Technology Inc. PIC16F627A/628A/648A Standard Operating Conditions (unless otherwise stated) Operating temperature - +125 C for extended Min† ...
Page 138
... XT, HS and LP osc SS PIN DD configuration V I =8.5 mA, V =4.5 V, - =7.0 mA, V =4.5 V, +85 to +125 =-3.0 mA, V =4.5 V, - =-2.5 mA, V =4 +125 C V RA4 pin PIC16F627A/628A/648A, PIC16LF627A/628A/648A pF In XT, HS and LP modes when external clock used to drive OSC1. pF 2004 Microchip Technology Inc. ...
Page 139
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section 13.7 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 2004 Microchip Technology Inc. PIC16F627A/628A/648A PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 140
... V = 3.0V to 5.5V DD -85° to +125° 2.0V to 3.0V DD -40° to +85°C s Units Comments LSb Low Range (VRR = 1) LSb High Range (VRR = 0) LSb Low Range (VRR = 1) LSb High Range (VRR = 0) s output signal on RA2 to REF 2004 Microchip Technology Inc. ...
Page 141
... Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low FIGURE 17-3: LOAD CONDITIONS LOAD CONDITION 1 PIN R = 464 for all pins except OSC2 for OSC2 output 2004 Microchip Technology Inc. PIC16F627A/628A/648A T osc LOAD CONDITION PIN V SS Preliminary Time OSC1 T0CKI ...
Page 142
... XT and RC Osc mode ns HS, EC Osc mode s LP Osc mode ns RC Osc mode ns XT Osc mode ns HS Osc mode s LP Osc mode ns INTOSC mode (fast) s INTOSC mode (slow 4/F CY OSC ns XT oscillator, T L/H duty OSC cycle — 5.0V DD 2004 Microchip Technology Inc. ...
Page 143
... F14 T Oscillator Wake-up from Sleep IOSCST start-up time FIGURE 17-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O PIN (INPUT) I/O PIN OLD VALUE (OUTPUT) 2004 Microchip Technology Inc. PIC16F627A/628A/648A Min Typ Max Units — 4 — MHz — — 1 — — ...
Page 144
... PIC16F62X — PIC16LF62X — PIC16F62X — PIC16LF62X — — PIC16F62X Tosc+200 ns* PIC16LF62X Tosc+400 ns* 0 PIC16F62X — PIC16LF62X — 100* 200 Preliminary 2004 Microchip Technology Inc. Typ† Max Units 75 200* ns — 400 200* ns — 400 100* ns — 200 100* ns — ...
Page 145
... Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI RB6/T1OSO/T1CKI TMR0 OR TMR1 2004 Microchip Technology Inc. PIC16F627A/628A/648A V BOR 35 Min Typ† Max ...
Page 146
... N = prescale value ( — — — — — ns — — ns (1) — kHz — 7Tosc — 2004 Microchip Technology Inc. ...
Page 147
... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Min Typ† Max Units 0.5T + 20* — ...
Page 148
... PIC16F627A/628A/648A NOTES: DS40044B-page 146 Preliminary 2004 Microchip Technology Inc. ...
Page 149
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Not Available at this time. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Preliminary DS40044B-page 147 ...
Page 150
... PIC16F627A/628A/648A NOTES: DS40044B-page 148 Preliminary 2004 Microchip Technology Inc. ...
Page 151
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2004 Microchip Technology Inc. PIC16F627A/628A/648A EXAMPLE PIC16F627A-I/P 0210017 EXAMPLE PIC16F628A -E/SO 0210017 EXAMPLE PIC16F648A -I/SS 0210017 EXAMPLE ...
Page 152
... L p MILLIMETERS MIN NOM MAX 18 2.54 3.56 3.94 4.32 2.92 3.30 3.68 0.38 7.62 7.94 8.26 6.10 6.35 6.60 22.61 22.80 22.99 3.18 3.30 3.43 0.20 0.29 0.38 1.14 1.46 1.78 0.36 0.46 0.56 7.87 9.40 10. 2004 Microchip Technology Inc. ...
Page 153
... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 2004 Microchip Technology Inc. PIC16F627A/628A/648A Units ...
Page 154
... Preliminary A2 MILLIMETERS MIN NOM MAX 20 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.18 5.11 5.25 5.38 7.06 7.20 7.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0. 2004 Microchip Technology Inc. ...
Page 155
... Chamfer Mold Draft Angle Top *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC equivalent: M0-220 Drawing No. C04-114 2004 Microchip Technology Inc. PIC16F627A/628A/648A EXPOSED METAL PADS D1 D ...
Page 156
... PIC16F627A/628A/648A NOTES: DS40044B-page 154 Preliminary 2004 Microchip Technology Inc. ...
Page 157
... DEVICE DIFFERENCES The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Device Flash Program PIC16F627A 1024 x 14 PIC16F628A 2048 x 14 PIC16F648A 4096 x 14 Preliminary Memory RAM EEPROM Data Data 224 x 8 128 x 8 ...
Page 158
... These differences may cause this device to perform differently in your application than the earlier version of this device. Preliminary MIGRATING FROM OTHER PICmicro DEVICES web site for availability web site for availability 2004 Microchip Technology Inc. ...
Page 159
... MPLAB C18 C Compiler: TBD Note: Please read all associated README.TXT files that are supplied with the develop- ment tools. These “read me” files will discuss product support and any known limitations. 2004 Microchip Technology Inc. PIC16F627A/628A/648A Preliminary DS40044B-page 157 ...
Page 160
... PIC16F627A/628A/648A NOTES: DS40044B-page 158 Preliminary 2004 Microchip Technology Inc. ...
Page 161
... Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2004 Microchip Technology Inc. PIC16F627A/628A/648A SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...
Page 162
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS40044B-page 160 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS40044B Preliminary 2004 Microchip Technology Inc. ...
Page 163
... CCPR1H Register............................................... 55 CCPR1L Register ............................................... 55 CCP2 .......................................................................... 55 Compare Mode. See Compare PWM Mode. See PWM Timer Resources......................................................... 55 CCP1CON Register CCP1M3:CCP1M0 Bits ............................................... 55 2004 Microchip Technology Inc. PIC16F627A/628A/648A CCP1X:CCP1Y Bits.................................................... 55 CCP2CON Register CCP2M3:CCP2M0 Bits .............................................. 55 CCP2X:CCP2Y Bits.................................................... 55 Clocking Scheme/Instruction Cycle .................................... 13 CLRF Instruction............................................................... 115 CLRW Instruction.............................................................. 116 CLRWDT Instruction ...
Page 164
... Package Marking Information ........................................... 149 Packaging Information ...................................................... 149 PCL and PCLATH............................................................... 28 Stack ........................................................................... 28 PCON Register ................................................................... 27 PICkit 1 Flash Starter Kit .................................................. 129 PICSTART Plus Development Programmer..................... 128 PIE1 Register...................................................................... 25 Pin Functions RC6/TX/CK ........................................................... 69–86 RC7/RX/DT........................................................... 69–86 PIR1 Register ..................................................................... 26 Port RB Interrupt............................................................... 105 PORTA ............................................................................... 31 PORTB ............................................................................... 36 Preliminary 2004 Microchip Technology Inc. ...
Page 165
... Q-Clock ............................................................................... 59 Quick-Turnaround-Production (QTP) Devices ...................... Oscillator ....................................................................... 96 RC Oscillator Mode Block Diagram............................................................. 96 Registers Maps PIC16F627A ................................................. 16, 17 PIC16F628A ................................................. 16, 17 Reset................................................................................... 97 RETFIE Instruction............................................................ 120 RETLW Instruction ............................................................ 121 RETURN Instruction ......................................................... 121 Revision History ................................................................ 155 RLF Instruction.................................................................. 121 RRF Instruction ................................................................. 122 S Serial Communication Interface (SCI) Module, See USART Serialized Quick-Turnaround-Production (SQTP) Devices ...
Page 166
... Synchronous Master Transmission............................. 83 Synchronous Slave Mode ........................................... 86 Synchronous Slave Reception .................................... 87 Synchronous Slave Transmit ...................................... 86 V Voltage Reference Configuration............................................................... 67 Voltage Reference Module.......................................... 67 W Watchdog Timer (WDT) .................................................... 106 WWW, On-Line Support........................................................ 3 X XORLW Instruction ........................................................... 124 XORWF Instruction ........................................................... 124 DS40044B-page 164 Preliminary 2004 Microchip Technology Inc. ...
Page 167
... The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. PIC16F627A/628A/648A /XX XXX ...
Page 168
... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/26/04 2004 Microchip Technology Inc. ...