PIC12C672-10/SM Microchip Technology, PIC12C672-10/SM Datasheet - Page 56

• Manufacturer Part Number: PIC12C672-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC12C672-10/SMR; PIC12C672-10/SMR

PIC12C67X
9.2.5
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at V
Section 13.0 for information on variation over voltage
and temperature.
In addition, a calibration instruction is programmed into
the last address of the program memory which contains
the calibration value for the internal RC oscillator. This
value is programmed as a RETLW XX instruction where
XX is the calibration value. In order to retrieve the cali-
bration value, issue a CALL YY instruction where YY is
the last location in program memory (03FFh for the
PIC12C671 and the PIC12CE673, 07FFh for the
PIC12C672 and the PIC12CE674). Control will be
returned to the user’s program with the calibration
value loaded into the W register. The program should
then perform a MOVWF OSCCAL instruction to load the
value into the internal RC oscillator trim register.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. Bits <7:4>, CAL<3:0> are
used for fine calibration, while bit 3, CALFST, and bit 2,
CALSLW, are used for more coarse adjustment. Adjust-
ing CAL<3:0> from 0000 to 1111 yields a higher clock
speed. Set CALFST = 1 for greater increase in fre-
quency or set CALSLW = 1 for greater decrease in fre-
quency. Note that bits 1 and 0 of OSCCAL are
unimplemented and should be written as 0 when mod-
ifying OSCCAL for compatibility with future devices.
9.2.6
The PIC12C67X can be configured to provide a clock
out signal (CLKOUT) on pin 3 when the configuration
word address (2007h) is programmed with F
F
EXTRC. The oscillator frequency, divided by 4, can be
used for test purposes or to synchronize other logic.
DS30561B-page 56
OSC
Note:
1, and F
INTERNAL 4 MHz RC OSCILLATOR
CLKOUT
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
OSC
0, equal to 101 for INTRC or 111 for
DD
= 5V and 25°C. See
OSC
2,
9.3
The PIC12C67X differentiates between various kinds
of reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), MCLR Reset, WDT
Reset, and MCLR Reset during SLEEP. They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different reset situations,
as indicated in Table 9-5. These bits are used in
software to determine the nature of the reset. See
Table 9-6 for a full description of reset states of all
registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 9-6.
The PIC12C67X has a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
When MCLR is asserted, the state of the OSC1/CLKIN
and CLKOUT/OSC2 pins are as follows:
TABLE 9-3:
EXTRC, CLKOUT
on OSC2
EXTRC, OSC2 is
I/O
INTRC, CLKOUT
on OSC2
INTRC, OSC2 is
I/O
Oscillator Mode
Reset
CLKIN/CLKOUT PIN STATES
WHEN MCLR ASSERTED
OSC1 pin is
tristated and
driven by external
circuit
OSC1 pin is
tristated and
driven by external
circuit
OSC1 pin is
tristate input
OSC1 pin is
tristate input
OSC1/CLKIN Pin OSC2/CLKout Pin
1999 Microchip Technology Inc.
OSC2 pin is driven
low
OSC2 pin is
tristate input
OSC2 pin is driven
low
OSC2 pin is
tristate input